Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 47 of 156
Table 44. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 FAULTSIGN
1
When this bit is set to Logic 1, the FAULTSIGN flag set creates a pending ADE interrupt to the 8052 core.
4 VARSIGN
2
When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 RNOLOAD
2
When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE5566 and ADE5569.
2
This function is not available in the ADE5166 and ADE5566.
Table 45. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit Interrupt Enable Bit Description
7
CF2
When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
4 REOF
1
When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
1 REHF
1
When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE5166 and ADE5566.
Table 46. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
4 PKI When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
3 PKV When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
2 CYCEND When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
1 ZXTO When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
0 ZX When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE5166/ADE5169/ADE5566/ADE5569 has two fully dif-
ferential voltage input channels. The maximum differential input
voltage for the V
P
/V
N
, I
PA
/I
N
, I
PB
/I
N
, and I
P
/I
N
input pairs is ±0.5 V.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain
selections are made by writing to the gain register (see Table 38
and Figure 41).
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
PGA2 GAIN SELECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
PGA1 GAIN SELECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
RESERVED
*REGISTER CONTENTS SHOW POWER-ON DEFAU
LTS.
ADDR:
0x1B
CFSIGN_OPT
07411-019
Figure 41. Analog Gain Register
Bit 2 to Bit 0 select the gain for the PGA in the current channel,
and Bit 7 to Bit 5 select the gain for the PGA in the voltage
channel. Figure 42 shows how a gain selection for the current
channel is made using the gain register.
K × V
IN
I
P
, I
Px
I
IN
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
GAIN[7:0]
GAIN (K)
SELECTION
V
IN
07411-018
Figure 42. PGA in Current Channel