Datasheet

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ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet

Rev. D | Page 52 of 156

FAULT DETECTION (ADE5166/ADE5169 ONLY)

The ADE5166/ADE5169 incorporate a fault detection scheme

that warns of fault conditions and allows accurate measurement to

continue during a fault event. (This feature is not available in the

ADE5566/ADE5569.) The ADE5166/ADE5169 do this by con-

tinuously monitoring both current inputs (I

and I

). For ease of

understanding, these currents are referred to as phase and neutral

(return) currents. In the ADE5166/ADE5169, a fault condition is

defined when the difference between I

and I

is greater than

6.25% of the active channel caused by amplitude or phase. If a

fault condition is detected and the inactive channel is larger than

the active channel, the ADE5166/ ADE5169 automatically switch

current measurement to the inactive channel. During a fault, the

active, reactive, and apparent power and the I

rms

are generated

using the larger of the two cur-rents. On power-up, I

is the

current input selected for active, reactive, and apparent power

and I

rms

calculations.

To pre vent a false alarm, averaging is done for the fault detection,

and a fault condition is detected approximately one second after

the event. The fault detection is automatically disabled when the

voltage signal is less than 0.3% of the full-scale input range. This

eliminates false detection of a fault due to noise at light loads.

Because the ADE5166/ADE5169 look for a difference between

the voltage signals on I

and I

, it is important that both current

transducers be closely matched.

Channel Selection Indication

The current channel selected for measurement is indicated

by the ICHANNEL bit (Bit 7) in the ACCMODE register

(Address 0x0F). When Bit 7 is cleared, I

is selected; when Bit 7

is set, I

is selected. The ADE5166/ADE5169 automatically switch

from one channel to the other and report the channel configuration

in the ACCMODE register.

The current channel selected for measurement can also be forced.

Setting the SEL_I_CH bits (Bits[5:4]) in the CALMODE register

(Address 0x3D) to 01 or 10 selects I

and I

, respectively. When

both bits are cleared or set, the current channel used for measure-

ment is selected automatically, based on the fault detection.

Fault Indication

The ADE5166/ADE5169 provide an indication of the part going

into or out of a fault condition. The new fault condition is indicated

by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR

(MIRQSTL, Address 0xDC).

When the FAULTSIGN bit (Bit 6) in the ACCMODE register

(Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt

Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is

entering a fault condition or a normal condition.

When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable 1

SFR (MIRQENL, Address 0xD9) and the FAULTSIGN flag (Bit 5)

in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set,

the 8052 core has a pending ADE interrupt.

Fault with Active Input Greater Than Inactive Input

If I

is the active current input (that is, I

is being used for

billing), and the voltage signal on I

(inactive input) falls below

93.75% of I

, and the FAULTSIGN bit (Bit 6) of the ACCMODE

in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.

Both analog inputs are filtered and averaged to prevent false

triggering of this logic output. As a consequence of the filtering,

there is a time delay of approximately 3 sec on the logic output

after the fault event. The FAULTSIGN flag is independent of

any activity. Because I

is the active input and it is still greater

than I

, billing is maintained on I

; that is, no swap to the I

input occurs. I

remains the active input.

Fault with Inactive Input Greater Than Active Input

If the difference between I

(the inactive input) and I

(the active

input that is being used for billing) becomes greater than 6.25%

of I

, and the FAULTSIGN bit (Bit 6) in the ACCMODE register

(Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Inter-

rupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. The I

analog

input becomes the active input. Again, a time constant of about

3 sec is associated with this swap. I

does not swap back to the

active channel until I

is greater than I

and the difference

between I

and I

, in this order, becomes greater than 6.25% of I

However, if the FAULTSIGN bit (Bit 6) in the ACCMODE register

(Address 0x0F) is set, the FAULTSIGN flag (Bit 5) in the Interrupt

Status 1 SFR (MIRQSTL, Address 0xDC) is set as soon as I

within 6.25% of I

. This threshold eliminates concerns about

potential chatter between I

and I

calibration.

Calibration Concerns

Typically, when a meter is calibrated, the voltage and current cir-

cuits are separated (see Figure 49). Current passes through only

the phase circuit or the neutral circuit. Figure 49 shows current

being passed through the phase circuit. This is the preferred option

because the ADE5166/ADE5169 start billing on the I

input on

power-up. The phase circuit, CT, is connected to I

in the diagram.

Because the current sensors are not perfectly matched, it is impor-

tant to match current inputs. The ADE5166/ADE5169 provide a

gain calibration register for I

, IBGAIN (Address 0x1C). IBGAIN

is a 12-bit, signed, twos complement register that provides a gain

resolution of 0.0244%/LSB.

AGND

PHASE

NEUTRAL

TEST

CURRENT

240V rms

07411-025

–

Figure 49. Fault Conditions for Inactive Input Greater Than Active Input