Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 64 of 156
POSPOS
INTERRUPT STATUS REGISTERS
NEG
APSIGN FLAG
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
ACTIVE ENERGY
APNOLOAD APNOLOAD
07411-044
Figure 69. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE5166/ADE5169/ADE5566/ADE5569 circuitry
has a pulse output whose frequency is proportional to active
power (see the Active Power Calculation section). This pulse
frequency output uses the calibrated signal from the WGAIN
register (Address 0x1D) output, and its behavior is consistent
with the setting of the active energy accumulation mode in the
ACCMODE register (Address 0x0F). The pulse output is active
low and should preferably be connected to an LED, as shown in
Figure 80.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumu-
lation of the ADE5166/ADE5169/ADE5566/ADE5569 can be
synchronized to the voltage channel zero crossing so that active
energy can be accumulated over an integral number of half-line
cycles. The advantage of summing the active energy over an integer
number of line cycles is that the sinusoidal component in the active
energy is reduced to 0. This eliminates any ripple in the energy
calculation. Energy is calculated more accurately and more quickly
because the integration period can be shortened. By using this
mode, the energy calibration can be greatly simplified, and the
time required to calibrate the meter can be significantly reduced.
In the line cycle active energy accumulation mode, the ADE5166/
ADE5169/ADE5566/ADE5569 accumulate the active power signal
in the LWATTHR register (Address 0x03) for an integral number
of line cycles, as shown in Figure 70. The number of half-line cycles
is specified in the LINCYC register (Address 0x12).
The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate
active power for up to 65,535 half-line cycles. Because the active
power is integrated on an integral number of line cycles, the
CYCEND flag (Bit 2) in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE) is set at the end of an active energy accumulation
line cycle. If the CYCEND enable bit (Bit 2) in the Interrupt
Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the CYCEND status bit is cleared (see the Energy Measurement
Interrupts section). Another calibration cycle starts as soon as the
CYCEND flag is set. If the LWATTHR register (Address 0x03) is
not read before a new CYCEND flag is set, the LWATTHR
register is overwritten by a new value.
WDIV[7:0]WATTOS[15:0]
WGAIN[11:0]
LPF1
+
+
LWATTHR[23:0]
ACCUMULATE
ACTIVE ENERGY IN
INTERNAL REGISTER
AND UPDATE THE
LWATTHR REGISTER
AT THE END OF LINCYC
HALF-LINE CYCLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-046
Figure 70. Line Cycle Active Energy Accumulation Mode