Datasheet
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 80 of 156
8052 MCU CORE ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 have an 8052 MCU
core and use the 8051 instruction set. Some of the standard 8052
peripherals, such as the UART, have been enhanced. This section
describes the standard 8052 core and enhancements that have
been made to it in the ADE5166/ADE5169/ADE5566/ADE5569.
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and all
on-chip peripherals. See Figure 81 for a block diagram showing
the programming model of the ADE5166/ADE5169/ADE5566/
ADE5569 via the SFR area.
All registers except the program counter (PC), instruction register
(IR), and the four general-purpose register banks reside in the
SFR area. The SFRs include control, configuration, and data
registers that provide an interface between the CPU and all on-
chip peripherals.
ENERGY
MEASUREMENT
PC
62kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8051-COMPATIBLE
CORE
2kB XRAM
OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
TIMERS
BATTERY
ADC
LCD DRIVER
TEMPERATURE
ADC
RTC
POWER
MANAGEMENT
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
IR
256 BYTES
GENERAL-
PURPOSE
RAM
REGISTER
BANKS
07411-056
Figure 81. Block Diagram Showing Programming Model via the SFRs
MCU REGISTERS
The registers used by the MCU are summarized in Table 57.
Table 57. 8051 SFRs
Table 58. Program Status Word SFR (PSW, Address 0xD0)
Bit Bit
Address
Mnemonic Description
7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions.
5 0xD5 F0 General-purpose flag available to the user.
[4:3] 0xD4,
0xD3
RS1, RS0 Register bank select bits.
RS1 RS0 Selected Bank
0
0
0
0 1 1
1 0 2
1 1 3
2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
1 0xD1 F1 General-purpose flag available to the user.
0 0xD0 P Parity bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
SFR Address Bit Addressable Description
ACC
0xE0
Yes
Accumulator.
B 0xF0 Yes Auxiliary math.
PSW 0xD0 Yes Program status word (see Table 58).
PCON 0x87 No Program control (see Table 59).
DPL 0x82 No Data pointer low (see Table 60).
DPH 0x83 No Data pointer high (see Table 61).
DPTR 0x82 and 0x83 No Data pointer (see Table 62).
SP 0x81 No Stack pointer (see Table 63).
SPH 0xB7 No Stack pointer high (see Table 64).
STCON 0xBF No Stack boundary (see Table 65).
CFG 0xAF No Configuration (see Table 66).