Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 93 of 156
INTERRUPT SYSTEM
The unique power management architecture of the ADE5166/
ADE5169/ADE5566/ADE5569 includes an operating mode
(PSM2) where the 8052 MCU core is shut down. Events can be
configured to wake the 8052 MCU core from the PSM2 operating
mode. A distinction is drawn here between events that can trigger
the wake-up of the 8052 MCU core and events that can trigger
an interrupt when the MCU core is active. Events that can wake
the core are referred to as wake-up events, whereas events that
can interrupt the program flow when the MCU is active are
called interrupts. See the 3.3 V Peripherals and Wake-Up Events
section to learn more about events that can wake the 8052 core
from PSM2 mode.
The ADE5166/ADE5169/ADE5566/ADE5569 provide 12 inter-
rupt sources with three priority levels. The power management
interrupt is at the highest priority level. The other two priority
levels are configurable through the interrupt priority SFR (IP,
Address 0xB8) and the Interrupt Enable and Priority 2 SFR
(IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
PRIORITY 1
PRIORITY 0
HIGH
LOW
07411-062
Figure 87. Standard 8052 Interrupt Priority Levels
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed (see the
Interrupt Priority section).
INTERRUPT ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 possess advanced
power supply management features. To ensure a fast response to
time-critical power supply issues, such as a loss of line power,
the power supply management interrupt should be able to inter-
rupt any interrupt service routine. To enable the user to have full
use of the standard 8052 interrupt priority levels, an additional
priority level is added for the power supply management (PSM)
interrupt. The PSM interrupt is the only interrupt at this highest
interrupt priority level.
PRIORITY 1
PRIORITY 0
PSM
HIGH
LOW
07411-063
Figure 88. Interrupt Architecture
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried out via four interrupt-related SFRs, which are discussed in this section.
Table 80. Interrupt SFRs
SFR Address Default Bit Addressable Description
IE 0xA8 0x00 Yes Interrupt enable (see Table 81).
IP 0xB8 0x00 Yes Interrupt priority (see Table 82).
IEIP2 0xA9 0xA0 No Interrupt Enable and Priority 2 (see Table 83).
WDCON 0xC0 0x10 Yes Watchdog timer (see Table 88 and the Writing to the Watchdog Timer SFR
(WDCON, Address 0XC0) section).
Table 81. Interrupt Enable SFR (IE, Address 0xA8)
Bit Bit Address Mnemonic Description
7 0xAF EA Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
6 0xAE ETEMP Enables the temperature ADC interrupt. Set by the user.
5 0xAD ET2 Enables the Timer 2 interrupt. Set by the user.
4 0xAC ES Enables the UART serial port interrupt. Set by the user.
3 0xAB ET1 Enables the Timer 1 interrupt. Set by the user.
2 0xAA EX1 Enables the External Interrupt 1 (
INT1
). Set by the user.
1 0xA9 ET0 Enables the Timer 0 interrupt. Set by the user.
0 0xA8 EX0 Enables External Interrupt 0 (
INT0
). Set by the user.