Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 98 of 156
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE5166/ADE5169/ADE5566/
ADE5569 enter an erroneous state, possibly due to a program-
ming error or electrical noise. The watchdog is enabled, by default,
with a timeout of 2 sec and creates a system reset if not cleared
within 2 sec. The watchdog function can be disabled by clearing
the watchdog enable bit (WDE, Bit 1) in the watchdog timer SFR
(WDCON, Address 0xC0).
The watchdog circuit generates a system reset or interrupt (WDS,
Bit 2) if the user program fails to set the WDE bit within a pre-
determined amount of time (set by the PRE bits, Bits[7:4]).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the XTAL1 and XTAL2 pins.
The WDCON SFR can be written to by user software only if the
double write sequence described in Table 88 is initiated on every
write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog,
a watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0xF7FF of
the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is
forced to 0, and the WDE bit is forced to 1. Note that the sequence
for configuring the flash protection bits must be followed to
modify the watchdog protection bit at Address 0xF7FF (see the
Protecting the Flash Memory section).
Table 88. Watchdog Timer SFR (WDCON, Address 0xC0)
Bit Address Mnemonic Default Description
[7:4] 0xC7 to 0xC4 PRE 7 Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
clock (32.768 kHz). The PRE bits determine which of the upper bits of the counter are used
as the watchdog output, as follows:
XTAL1
t
PRE
WATCHDOG
9
2
2 ×=
PRE Result (Watchdog Timeout)
0000 15.6 ms
0001 31.2 ms
0010
62.5 ms
0011 125 ms
0100 250 ms
0101 500 ms
0110 1 sec
0111 2 sec
1000 0 sec, automatic reset
1001 0 sec, serial download reset
1010 to 1111 Not a valid selection
3 0xC3 WDIR 0 Watchdog interrupt response bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
2 0xC2 WDS 0 Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the
RESET
pin.
1 0xC1 WDE 1 Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0 0xC0 WDWR 0 Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address
0XC0) section).