Datasheet

REV. A
ADE7757
–3–
TIMING CHARACTERISTICS
1, 2
Parameter A, B Versions Unit Test Conditions/Comments
t
1
3
244 ms F1 and F2 Pulse Width (Logic Low).
t
2
See Table II sec Output Pulse Period. See Transfer Function section.
t
3
1/2 t
2
sec Time between F1 Falling Edge and F2 Falling Edge.
t
4
3, 4
173 ms CF Pulse Width (Logic High).
t
5
See Table III sec CF Pulse Period. See Transfer Function section.
t
6
2 µs Minimum Time between F1 and F2 Pulses.
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.
4
The CF pulse is always 35 µs in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.
(V
DD
= 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 kΩ,
0.5%  50 ppm/C, T
MIN
to T
MAX
= –40C to +85C, unless otherwise noted.)
F1
F2
CF
t
1
t
5
t
4
t
2
t
6
t
3
Figure 1. Timing Diagram for Frequency Outputs