Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 12 of 100
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T
MIN
to T
MAX
= −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams; see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions.
Table 3. I
2
C-Compatible Interface Timing Parameter
Standard Mode Fast Mode
Parameter Symbol Min Max Min Max Unit
SCL Clock Frequency f
SCL
0 100 0 400 kHz
Hold Time (Repeated) Start Condition t
HD;STA
4.0 0.6 μs
Low Period of SCL Clock
t
LOW
4.7
1.3
µs
High Period of SCL Clock t
HIGH
4.0 0.6 µs
Set-Up Time for Repeated Start Condition t
SU;STA
4.7 0.6 µs
Data Hold Time t
HD;DAT
0 3.45 0 0.9 µs
Data Setup Time t
SU ;DAT
250 100 ns
Rise Time of Both SDA and SCL Signals t
R
1000 20 300 ns
Fall Time of Both SDA and SCL Signals t
F
300 20 300 ns
Setup Time for Stop Condition t
SU;STO
4.0 0.6 µs
Bus Free Time Between a Stop and Start Condition t
BUF
4.7 1.3 µs
Pulse Width of Suppressed Spikes t
SP
N/A
1
50 ns
1
N/A means not applicable.
t
F
t
R
t
HD;DAT
t
HD;STA
t
HIGH
t
SU;STA
t
SU;DAT
t
F
t
HD;STA
t
SP
t
SU;STO
t
R
t
BUF
t
LOW
SDA
SCLK
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
08510-002
Figure 5. I
2
C-Compatible Interface Timing