Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 13 of 100
Table 4. SPI Interface Timing Parameters
Parameter Symbol Min Max Unit
SS to SCLK Edge
t
SS
50 ns
SCLK Period 0.4 4000
1
μs
SCLK Low Pulse Width t
SL
175 ns
SCLK High Pulse Width t
SH
175 ns
Data Output Valid After SCLK Edge t
DAV
100 ns
Data Input Setup Time Before SCLK Edge t
DSU
100 ns
Data Input Hold Time After SCLK Edge t
DHD
5 ns
Data Output Fall Time t
DF
20 ns
Data Output Rise Time t
DR
20 ns
SCLK Rise Time
t
SR
20
ns
SCLK Fall Time t
SF
20 ns
MISO Disable After SS Rising Edge
t
DIS
200 ns
SS High After SCLK Edge
t
SFS
0 ns
1
Guaranteed by design.
MSB LSB
LSB IN
INTERMEDIATE BITS
INTERMEDIATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DHD
t
DAV
t
DSU
t
SR
t
SF
t
DR
MSB IN
MOSI
MISO
SCLK
SS
08510-003
Figure 6. SPI Interface Timing