Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 14 of 100
Table 5. HSDC Interface Timing Parameter
Parameter Symbol Min Max Unit
HSA to HSCLK Edge t
SS
0 ns
HSCLK Period 125 ns
HSCLK Low Pulse Width t
SL
50 ns
HSCLK High Pulse Width t
SH
50 ns
Data Output Valid After HSCLK Edge
t
DAV
40
ns
Data Output Fall Time t
DF
20 ns
Data Output Rise Time t
DR
20 ns
HSCLK Rise Time t
SR
10 ns
HSCLK Fall Time t
SF
10 ns
HSD Disable After HSA Rising Edge
t
DIS
5
ns
HSA High After HSCLK Edge t
SFS
0 ns
MSB LSBINTERMEDI
ATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DAV
t
SR
t
SF
t
DR
HSD
HSCLK
HS
A
08510-004
Figure 7. HSDC Interface Timing
2mA I
OL
800µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
08510-005
Figure 8. Load Circuit for Timing Specifications