Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 17 of 100
Pin No. Mnemonic Description
18, 19, 22, 23 VN, VCP, VBP, VAP
Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is
referenced as the voltage channel in this document. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also
has an internal PGA.
24
AVDD
2.5 V output of the analog low dropout regulator (LDO). Decouple this pin with a 4.7 µF capacitor in
parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin.
25 AGND
Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the
analog ground plane or to the quietest ground reference in the system. Use this quiet ground
reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.
26 VDD
Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the
supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low
power mode), and PSM3 (sleep mode), when the ADE7868/ADE7878 is supplied from a battery,
maintain the supply voltage between 2.4 V and 3.7 V. Decouple this pin to AGND with a 10 µF
capacitor in parallel with a ceramic 100 nF capacitor. The only modes available on the ADE7858 and
ADE7854 are the PSM0 and PSM3 power modes.
27 CLKIN
Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal can be
connected across CLKIN and CLKOUT to provide a clock source for the ADE7854/ADE7858/
ADE7868/ADE7878. The clock frequency for specified operation is 16.384 MHz. See the Crystal
Circuit section for details on choosing a suitable crystal.
28 CLKOUT
A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this
table) to provide a clock source for the ADE7854/ADE7858/ADE7868/ADE7878.
29, 32
IRQ0, IRQ1 Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a
detailed presentation of the events that can trigger interrupts.
33, 34, 35
CF1, CF2,
CF3/HSCLK
Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the
CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for
operational and calibration purposes. The full-scale output frequency can be scaled by writing to the
CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion
section). CF3 is multiplexed with the serial clock output of the HSDC port.
36 SCLK/SCL
Serial Clock Input for SPI Port/Serial Clock Input for I
2
C Port. All serial data transfers are synchronized
to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a
clock source that has a slow edge transition time, for example, opto-isolator outputs.
37 MISO/HSD Data Out for SPI Port/Data Out for HSDC Port.
38
MOSI/SDA
Data In for SPI Port/Data Out for I
2
C Port.
39
SS/HSA
Slave Select for SPI Port/HSDC Port Active.
EP Exposed Pad
Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the
PCB to confer mechanical strength to the package. Connect the pads to AGND and DGND.