Datasheet
ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 36 of 100
PHASE A
CURRENT
ANGLE0
PHASE A
VOLTAGE
08510-031
Figure 47. Delay Between Phase A Voltage and Phase A Current Is
Stored in the ANGLE0 Register
When the ANGLESEL[1:0] bits are set to 01, the delays between
phase voltages are measured. The delay between Phase A voltage
and Phase C voltage is stored into the ANGLE0 register. The
delay between Phase B voltage and Phase C voltage is stored in
the ANGLE1 register, and the delay between Phase A voltage
and Phase B voltage is stored in the ANGLE2 register (see
Figure 48 for details).
When the ANGLESEL[1:0] bits are set to 10, the delays between
phase currents are measured. Similar to delays between phase
voltages, the delay between Phase A and Phase C currents is stored
into the ANGLE0 register, the delay between Phase B and Phase C
currents is stored in the ANGLE1 register, and the delay between
Phase A and Phase B currents is stored into the ANGLE2
register (see Figure 48 for details).
PHASE B PHASE CPHASE A
ANGLE2
ANGLE0
ANGLE1
0
8510-032
Figure 48. Delays Between Phase Voltages (Currents)
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
256 kHz) for 60 Hz systems. The delays between phase voltages
or phase currents are used to characterize how balanced the
load is. The delays between phase voltages and currents are
used to compute the power factor on each phase as shown in
the following Equation 5:
cosφ
x
= cos
kHz256
360
LINE
f
ANGLEx
(5)
where f
LINE
= 50 Hz or 60 Hz.
Period Measurement
The ADE7854/ADE7858/ADE7868/ADE7878 provide the
period measurement of the line in the voltage channel. Bits[1:0]
(PERSEL[1:0]) in the MMODE register select the phase voltage
used for this measurement. The period register is a 16-bit
unsigned register and updates every line period. Because of the
LPF1 filter (see Figure 43), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period register
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the register enables the measurement of line frequencies
as low as 3.9 Hz (256 kHz/2
16
). The period register is stable at
±1 LSB when the line is established and the measurement does
not change.
The following expressions can be used to compute the line
period and frequency using the period register:
sec
3E256
1
0]PERIOD[15:
T
L
(6)
]Hz[
1
3E256
0]PERIOD[15:
f
L
(7)
Phase Voltage Sag Detection
The ADE7854/ADE7858/ADE7868/ADE7878 can be pro-
grammed to detect when the absolute value of any phase voltage
drops below a certain peak value for a number of half-line cycles.
The phase where this event takes place is identified in Bits[14:12]
(VSPHASE[x]) of the PHSTATUS register. This condition is
illustrated in Figure 49.
PHASE A VOLTAGE
BIT 16 (SAG) IN
STATUS1[31:0]
VSPHASE[0] =
PHSTATUS[12]
IRQ1 PIN
FULL SCALE
SAGLVL[23:0]
FULL SCALE
SAGLVL[23:0]
SAGCYC[7:0] = 0x4
PHASE B VOLTAGE
VSPHASE[1] =
PHSTATUS[13]
STATUS[16] AND
PHSTATUS[13]
SET TO 1
08510-033
STATUS1[16] AND
PHSTATUS[12]
CANCELLED BY A
WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
SAGCYC[7:0] = 0x4