Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 38 of 100
PHASE A
CURRENT
PHASE B
CURRENT
BIT 24
OF IPEAK
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INT
O
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
END OF SECOND
PEAKCYC = 16 PERIOD
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF SECOND
PEAKCYC PERIOD
08510-035
Figure 51. Peak Level Detection
Figure 51 shows how the ADE78xx records the peak value on the
current channel when measurements on Phase A and Phase B are
enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).
PEAKCYC is set to 16, meaning that the peak measurement
cycle is four line periods. The maximum absolute value of Phase A
is the greatest during the first four line periods (PEAKCYC = 16),
so the maximum absolute value is written into the less signifi-
cant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of
the IPEAK register is set to 1 at the end of the period. This bit
remains at 1 for the duration of the second PEAKCYC period of
four line cycles. The maximum absolute value of Phase B is the
greatest during the second PEAKCYC period; therefore, the
maximum absolute value is written into the less significant
24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the
IPEAK register is set to 1 at the end of the period.
At the end of the peak detection period in the current channel,
Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
in the MASK1 register is set, the
IRQ1
interrupt pin is driven low
at the end of PEAKCYC period and Status Bit 23 (PKI) in the
STATUS1 register is set to 1. In a similar way, at the end of the
peak detection period in the voltage channel, Bit 24 (PKV) in the
STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1
register is set, the
IRQ1
interrupt pin is driven low at the end of
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
register is set to 1. To find the phase that triggered the interrupt,
one of either the IPEAK or VPEAK registers is read immediately
after reading the STATUS1 register. Next, the status bits are
cleared, and the
IRQ1
pin is set to high by writing to the
STATUS1 register with the status bit set to 1.
Note that the internal zero-crossing counter is always active. By
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the
first peak detection result is, therefore, not executed across a full
PEAKCYC period. Writing to the PEAKCYC register when the
PEAKSEL[2:0] bits are set resets the zero-crossing counter,
thereby ensuring that the first peak detection result is obtained
across a full PEAKCYC period.
Overvoltage and Overcurrent Detection
The ADE7854/ADE7858/ADE7868/ADE7878 detect when the
instantaneous absolute value measured on the voltage and
current channels becomes greater than the thresholds set in the
OVLVL and OILVL 24-bit unsigned registers. If Bit 18 (OV) in
the MASK1 register is set, the
IRQ1
interrupt pin is driven low
in case of an overvoltage event. There are two status flags set
when the
IRQ1
interrupt pin is driven low: Bit 18 (OV) in the
STATUS1 register and one of Bits[11:9] (OVPHASE[2:0]) in the
PHSTATUS register to identify the phase that generated the
overvoltage. The Status Bit 18 (OV) in the STATUS1 register
and all Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register
are cleared, and the
IRQ1
pin is set to high by writing to the
STATUS1 register with the status bit set to 1. Figure 52 presents
overvoltage detection in Phase A voltage.
OVLVL[23:0]
BIT 18 (OV) OF
STATUS1
BIT 9 (OVPHASE)
OF PHSTATUS
PHASE
A
VOLTAGE CHANNEL
OVERVOLTAGE
DETECTED
STATUS1[18] AND
PHSTATUS[9]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
0
8510-036
Figure 52. Overvoltage Detection
Whenever the absolute instantaneous value of the voltage goes
above the threshold from the OVLVL register, Bit 18 (OV) in
the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Bit 18 (OV) of the STATUS1 register and
Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled
when the STATUS1 register is written with Bit 18 (OV) set to 1.
The recommended procedure to manage overvoltage events is
the following:
1.
Enable OV interrupts in the MASK1 register by setting
Bit 18 (OV) to 1.
2.
When an overvoltage event happens, the
IRQ1
interrupt
pin goes low.
3.
The STATUS1 register is read with Bit 18 (OV) set to 1.
4.
The PHSTATUS register is read, identifying on which
phase or phases an overvoltage event happened.