Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 39 of 100
5. The STATUS1 register is written with Bit 18 (OV) set to 1.
In this moment, Bit OV is erased and also all Bits[11:9]
(OVPHASE[2:0]) of the PHSTATUS register.
In case of an overcurrent event, if Bit 17 (OI) in the MASK1
register is set, the
IRQ1
interrupt pin is driven low. Immediately,
Bit 17 (OI) in the STATUS1 register and one of Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register, which identify
the phase that generated the interrupt, are set. To f ind the
phase that triggered the interrupt, the PHSTATUS register
is read immediately after reading the STATUS1 register. Next,
Status Bit 17 (OI) in the STATUS1 register and Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register are cleared and the
IRQ1
pin is set to high by writing to the STATUS1 register with
the status bit set to 1. The process is similar with overvoltage
detection.
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL), and overcurrent,
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs:
+5,928,256 (0x5A7540). When the OVLVL or OILVL register is
equal to this value, the overvoltage or overcurrent conditions
are never detected. Writing 0x0 to these registers signifies the
overvoltage or overcurrent conditions are continuously detected,
and the corresponding interrupts are permanently triggered.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 36, OILVL and
OVLVL registers are accessed as 32-bit registers with the eight
MSBs padded with 0s.
Neutral Current Mismatch—ADE7868, ADE7878
Neutral current mismatch is available in the ADE7868 and
ADE7878 only. In 3-phase systems, the neutral current is equal
to the algebraic sum of the phase currents
I
N
(t) = I
A
(t) + I
B
(t) + I
C
(t)
If there is a mismatch between these two quantities, then a
tamper situation may have occurred in the system.
The ADE7868/ADE7878 compute the sum of the phase
currents adding the content of the IAWV, IBWV, and ICWV
registers, and storing the result into the ISUM 28-bit signed
register: I
SUM
(t) = I
A
(t) + I
B
(t) + I
C
(t). ISUM is computed every
125 µs (8 kHz frequency), the rate at which the current samples
are available, and Bit 17 (DREADY) in the STATUS0 register is
used to signal when the ISUM register can be read. See the
Digital Signal Processor section for more details on Bit DREADY.
To recover I
SUM
(t) value from the ISUM register, use the
following expression:
FS
MAX
SUM
I
ADC
ISUM[27:0]
tI ×=)(
where:
ADC
MAX
= 5,928,256, the ADC output when the input is at full
scale.
I
FS
is the full-scale ADC phase current.
The ADE7868/ADE7878 compute the difference between the
absolute values of ISUM and the neutral current from the
INWV register, take its absolute value and compare it against
the ISUMLVL threshold. If
ISUMLVLINWV
ISUM
≤−
,
then it is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly. If
ISUMLVLINWVISUM >−
, then a tamper situation may
have occurred, and Bit 20 (MISMTCH) in the STATUS1 register
is set to 1. An interrupt attached to the flag can be enabled by
setting Bit 20 (MISMTCH) in the MASK1 register. If enabled,
the
IRQ1
pin is set low when Status Bit MISMTCH is set to 1.
The status bit is cleared and the
IRQ1
pin is set back to high by
writing to the STATUS1 register with Bit 20 (MISMTCH) set to 1.
If
ISUMLVLINWVISUM ≤−
, then MISMTCH = 0
If
ISUMLVLINWVISUM >−
, then MISMTCH = 1
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an
absolute value, always set ISUMLVL as a positive number,
somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
the same scale of the current ADCs outputs, so writing
+5,928,256 (0x5A7540) to the ISUMLVL register puts the
mismatch detection level at full scale; see the Current Channel
ADC section for details. Writing 0x000000, the default value, or
a negative value, signifies the MISMTCH event is always triggered.
The right value for the application should be written into the
ISUMLVL register after power-up or after a hardware/software
reset to avoid continuously triggering MISMTCH events.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7868/ADE7878 work on 32-, 16-, or 8-bit
words and the DSP works on 28 bits. As presented in Figure 53,
ISUM, the 28-bit signed register, is accessed as a 32-bit register
with the four most significant bits padded with 0s.
31 28 27
BIT 27 IS A SIGN BIT
0
28-BIT SIGNED NUMBER0000
08510-250
Figure 53. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
Similar to the registers presented in Figure 35, the ISUMLVL
register is accessed as a 32-bit register with four most significant
bits padded with 0s and sign extended to 28 bits.
PHASE COMPENSATION
As described in the Current Channel ADC and Voltage Channel
ADC sections, the datapath for both current and voltages is the
same. The phase error between current and voltage signals
introduced by the ADE7854/ADE7858/ADE7868/ADE7878
is negligible. However, the ADE7854/ADE7858/ADE7868/
ADE7878 must work with transducers that may have inherent