Datasheet

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ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet

Rev. G | Page 42 of 100

08510-257

NUMBER OF PARTS

HOT TEMPERATURE COEFFICIENT (ppm/°C)

–50 –45 –40 –35 –30 –5 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50

Figure 58. Histogram of the Reference Drift from 25°C to 85°C

Because the reference is used for all ADCs, any x% drift in the

reference results in a 2x% deviation of the meter accuracy. The

reference drift resulting from temperature changes is usually very

small and, typically, much smaller than the drift of other

components on a meter.

The ADE7854/ADE7858/ADE7868/ADE7878 use the internal

voltage reference when Bit 0 (EXTREFEN) in the CONFIG2

reference is used when the bit is set to 1. Set the CONFIG2 register

during the PSM0 mode; its value is maintained during the PSM1,

PSM2, and PSM3 power modes.

DIGITAL SIGNAL PROCESSOR

The ADE7854/ADE7858/ADE7868/ADE7878 contain a fixed

function digital signal processor (DSP) that computes all powers

and rms values. It contains program memory ROM and data

memory RAM.

The program used for the power and rms computations is

stored in the program memory ROM and the processor executes

it every 8 kHz. The end of the computations is signaled by

setting Bit 17 (DREADY) to 1 in the STATUS0 register. An

interrupt attached to this flag can be enabled by setting Bit 17

(DREADY) in the MASK0 register. If enabled, the

IRQ0

pin is

set low and Status Bit DREADY is set to 1 at the end of the

computations. The status bit is cleared and the

IRQ0

pin is set

to high by writing to the STATUS0 register with Bit 17 (DREADY)

set to 1.

The registers used by the DSP are located in the data memory

RAM, at addresses between 0x4380 and 0x43BE. The width of

this memory is 28 bits. Within the DSP core, the DSP contains a

two stage pipeline. This means that when a single register needs

to be initialized, two more writes are required to ensure the

value has been written into RAM, and if two or more registers

need to be initialized, the last register must be written two more

times to ensure the value has been written into RAM.

As explained in the Power-Up Procedure section, at power-up

or after a hardware or software reset, the DSP is in idle mode.

No instruction is executed. All the registers located in the data

memory RAM are initialized at 0, their default values, and they

can be read/written without any restriction. The run register,

used to start and stop the DSP, is cleared to 0x0000. The run

code execution.

To protect the integrity of the data stored in the data memory

RAM of the DSP (addresses between 0x4380 and 0x43BE),

a write protection mechanism is available. By default, the

protection is disabled and registers placed between 0x4380 and

0x43BE can be written without restriction. When the protection

is enabled, no writes to these registers is allowed. Registers can

be always read, without restriction, independent of the write

protection state.

To enable the protection, write 0xAD to an internal 8-bit

to an internal 8-bit register located at Address 0xE7E3.

It is recommended to enable the write protection after the

registers have been initialized. If any data memory RAM based

change the value and then re-enable the protection. There is

no need to stop the DSP to change these registers.

To disable the protection, write 0xAD to an internal 8-bit

to an internal 8-bit register located at Address 0xE7E3.

The recommended procedure to initialize the ADE7854/

ADE7858/ADE7868/ADE7878 registers at power up is as

follows:

• Initialize the AIGAIN, BIGAIN, CIGAIN, and NIGAIN

registers.

• Start the DSP by setting run = 1.

• Initialize all the other data memory RAM registers. Write

the last register in the queue three times to ensure its

value was written into the RAM. Initialize all of the other

ADE7854/ADE7858/ADE7868/ADE7878 registers with the

exception of the CFMODE register.

• Read the energy registers xWATTHR, xFWATTHR,

xVARHR, xFVARHR, and xVAHR to erase their content

and start energy accumulation from a known state.

• Clear Bit 9 (CF1DIS), Bit 10 (CF2DIS), and Bit 11

(CF3DIS) in the CFMODE register to enable pulses at

the CF1, CF2, and CF3 pins. Do this initialization last,

so no spurious pulses are generated while the ADE7854/

ADE7858/ADE7868/ADE7878 are initialized.

• Enable the write protection by writing 0xAD to an internal

8-bit register located at Address 0xE7FE, followed by a write of

0x80 to an internal 8-bit register located at Address 0xE7E3.

• Read back all data memory RAM registers to ensure they

were initialized with the desired values.

• In the remote case that one or more registers are not initia-

lized correctly, disable the protection by writing 0xAD to