Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 48 of 100
If the phase currents and voltages contain only the fundamental
component, are in phase (that is φ
1
= γ
1
= 0), and they correspond
to full-scale ADC inputs, then multiplying them results in an
instantaneous power signal that has a dc component, V
1
× I
1
,
and a sinusoidal component, V
1
× I
1
cos(2ωt); Figure 65 shows
the corresponding waveforms.
INSTANTANEOU
S
POWER SIGNAL
INSTANTANEOUS
ACTIVE POWER
SIGNAL: V rms × I rms
p(t)= V rms × I rms – V rms × I rms × cos(2ωt)
0x3FED4D6
67,032,278
V rms × I rms
0x1FF6A6B =
33,516,139
0x000 0000
i(t) = √2×I rms×sin(ωt)
v(t) = √2×V rms×sin(ωt)
08510-043
Figure 65. Active Power Calculation
Because LPF2 does not have an ideal brick wall frequency
response (see Figure 66), the active power signal has some
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency.
Because the ripple is sinusoidal in nature, it is removed when
the active power signal is integrated over time to calculate the
energy.
0
–5
–10
–15
–20
–25
0.1 13 10
FREQUENCY (Hz)
MAGNITUDE (dB)
08510-103
Figure 66. Frequency Response of the LPF Used
to Filter Instantaneous Power in Each Phase
The ADE7854/ADE7858/ADE7868/ADE7878 store the
instantaneous total phase active powers into the AWATT,
BWATT, and CWATT registers. Their expression is




1k
FS
k
FS
k
I
I
V
V
xWATT
cos(φ
k
– γ
k
) × PMAX ×
4
2
1
(20)
where:
V
FS
, I
FS
are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 33,516,139; it is the instantaneous power computed
when the ADC inputs are at full scale and in phase.
The xWATT[23:0] waveform registers can be accessed using
various serial ports. Refer to the Waveform Sampling Mode
section for more details.
Fundamental Active Power Calculation—ADE7878 Only
The ADE7878 computes the fundamental active power using
a proprietary algorithm that requires some initializations function
of the frequency of the network and its nominal voltage measured
in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE
register must be set according to the frequency of the network in
which the ADE7878 is connected. If the network frequency is
50 Hz, clear this bit to 0 (the default value). If the network fre-
quency is 60 Hz, set this bit to 1. In addition, initialize the VLEVEL
24-bit signed register with a positive value based on the
following expression:
520,491
n
FS
V
V
VLEVEL
(21)
where:
V
FS
is the rms value of the phase voltages when the ADC inputs
are at full scale.
V
n
is the rms nominal value of the phase voltage.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7878 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the registers presented
in Figure 35, the VLEVEL 24-bit signed register is accessed as a
32-bit register with four most significant bits padded with 0s
and sign extended to 28 bits.
Table 14 presents the settling time for the fundamental active
power measurement.
Table 14. Settling Time for Fundamental Active Power
Input Signals
63% Full Scale 100% Full Scale
375 ms 875 ms
Active Power Gain Calibration
Note that the average active power result from the LPF2 output
in each phase can be scaled by ±100% by writing to the phase’s
watt gain 24-bit register (AWGAIN, BWGAIN, CWGAIN,
AFWGAIN, BFWGAIN, or CFWGAIN). The xWGAIN
registers are placed in each phase of the total active power
datapath, and the xFWGAIN (available for the ADE7878 only)
registers are placed in each phase of the fundamental active
power datapath. The watt gain registers are twos complement,
signed registers and have a resolution of 2
−23
/LSB. Equation 22
describes mathematically the function of the watt gain registers.








23
2
12
gisterReGainWatt
OutputLPF
DataPowe
r
Average
(22)