Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 56 of 100
Integration Time Under A Steady Load
The discrete time sample period (T) for the accumulation register
is 125 µs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs and a 90° phase difference between the vol-
tage and the current signal (the largest possible reactive power),
the average word value representing the reactive power is PMAX =
33,516,139 = 0x1FF6A6B. If t he VARTH R threshold is set at the
PMAX level, this means the DSP generates a pulse that is added
at the var-hour registers every 125 µs.
The maximum value that can be stored in the var-hour
accumulation register before it overflows is 2
31
− 1 or
0x7FFFFFFF. The integration time is calculated as
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec (38)
Energy Accumulation Modes
The reactive power accumulated in each var-hour accumulation
32-bit register (AVARHR, BVARHR, CVARHR, AFVARHR,
BFVARHR, and CFVARHR) depends on the configuration of
Bits[5:4] (CONSEL[1:0]) in the ACCMODE register, in correlation
with the watt-hour registers. The different configurations are
described in Table 19. Note that IA’/IB’/IC’ are the phase-shifted
current waveforms.
Table 19. Inputs to Var-Hour Accumulation Registers
CONSEL[1:0]
AVARHR,
AFVARHR
BVARHR,
BFVARHR
CVARHR,
CFVARHR
00
VA × IA’
VB × IB’
VC × IC’
01 VA × IA’ 0 VC × IC’
10 VA × IA’ VB × IB’ VC × IC’
VB = −VA − VC
11 VA × IA’ VB × IB’ VC × IC ’
VB = −VA
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine
how CF frequency output can be a generated function of the total
and fundamental reactive powers. While the var-hour accumu-
lation registers accumulate the reactive power in a signed
format, the frequency output can be generated in either the signed
mode or the sign adjusted mode function of VARACC[1:0]. See
the Energy-to-Frequency Conversion section for details.
Line Cycle Reactive Energy Accumulation Mode
As mentioned in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage
channel zero crossings so that reactive energy can be accu-
mulated over an integral number of half line cycles.
In this mode, the ADE7858/ADE7868/ADE7878 transfer the
reactive energy accumulated in the 32-bit internal accumulation
registers into the xVARHR or xFVARHR registers after an
integral number of line cycles, as shown in Figure 72. The
number of half line cycles is specified in the LINECYC register.
The line cycle reactive energy accumulation mode is activated by
setting Bit 1 (LVAR) in the LCYCMODE register. The total reactive
energy accumulated over an integer number of half line cycles
or zero crossings is available in the var-hour accumulation registers
after the number of zero crossings specified in the LINECYC reg-
ister is detected. When using the line cycle accumulation mode,
Bit 6 (RSTREAD) of the LCYCMODE register should be set to
Logic 0 because a read with the reset of var-hour registers is not
available in this mode.
ZERO-
CROSSING
DETECTION
(PHASE A)
ZERO-
CROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
ZERO-
CROSSING
DETECTION
(PHASE C)
LINECYC[15:0]
AVARHR[31:0]
ZXSEL[0] IN
LCYCMODE[7:0]
ZXSEL[1] IN
LCYCMODE[7:0]
ZXSEL[2] IN
LCYCMODE[7:0]
OUTPUT
FROM
TOTAL
REACTIVE
POWER
ALGORITHM
AVARGAIN
AVAROS
ACCUMULATOR
VARTHR[47:0]
32-BIT
REGISTER
08510-146
Figure 72. Line Cycle Total Reactive Energy Accumulation Mode
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero-crossings count during calibration.
For details on setting the LINECYC register and the Bit 5
(LENERGY) in the MASK0 interrupt mask register associated
with the line cycle accumulation mode, see the Line Cycle
Active Energy Accumulation Mode section.