Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 59 of 100
In the ADE7854/ADE7858/ADE7868/ADE7878, the phase
apparent powers are accumulated in the AVAHR, BVAHR, and
CVAHR 32-bit signed registers. The apparent energy register
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the apparent power is
positive.
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
the xVAHR registers changes, signifying one of these registers is
half full. As the apparent power is always positive and the xVAHR
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts
attached to Bit VAEHF in the STATUS0 register can be enabled by
setting Bit 4 in the MASK0 register. If enabled, the
IRQ0
pin is set
low and the status bit is set to 1 whenever one of the Energy
Registers xVAHR becomes half full. The status bit is cleared and
the
IRQ0
pin is set to high by writing to the STATUS0 register
with the corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
125 µs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs, the average word value representing the
apparent power is PMAX. If the VATHR threshold register is set
at the PMAX level, this means the DSP generates a pulse that
is added at the xVAHR registers every 125 µs.
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 2
31
− 1 or
0x7FFFFFFF. The integration time is calculated as
Time = 0x7FFF,FFFF × 125 s = 74 hr 33 min 55 sec (45)
Energy Accumulation Mode
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
in Table 20.
Table 20. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0] AVAHR BVAHR CVAHR
00 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
01 AVRMS × AIRMS 0 CVRMS × CIRMS
10 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
VB = −VA − VC
11 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
VB = −VA
Line Cycle Apparent Energy Accumulation Mode
As described in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage channel
zero crossings allowing apparent energy to be accumulated over an
integral number of half line cycles. In this mode, the ADE7854/
ADE7858/ADE7868/ADE7878transfer the apparent energy
accumulated in the 32-bit internal accumulation registers into
the xVAHR registers after an integral number of line cycles, as
shown in Figure 74. The number of half line cycles is specified
in the LINECYC register.
ZERO-
CROSSING
DETECTION
(PHASE A)
ZERO-
CROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
ZERO-
CROSSING
DETECTION
(PHASE C)
LINECYC[15:0]
AVAHR[31:0]
ZXSEL[0] IN
LCYCMODE[7:0]
ZXSEL[1] IN
LCYCMODE[7:0]
ZXSEL[2] IN
LCYCMODE[7:0]
AVAGAINAIRMS
AVRMS
ACCUMUL ATOR
VAHR[47:0]
32-BIT
REGISTER
08510-049
Figure 74. Line Cycle Apparent Energy Accumulation Mode