Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 64 of 100
POSPOS
VARNOLOAD
SIGN = POSITIVE
NEG
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
REACTIVE
POWER
ACTIVE
POWER
REACTIVE
ENERGY
REVRPx BIT
IN STATUS0
x
VARSIGN BIT
IN PHSIGN
08510-155
Figure 81. Reactive Power Accumulation in Sign Adjusted Mode
Sign of Sum-of-Phase Powers in the CFx Datapath
The ADE7854/ADE7858/ADE7868/ADE7878 have sign
detection circuitry for the sum of phase powers that are used in
the CFx datapath. As seen in the beginning of the Energy-to-
Frequency Conversion section, the energy accumulation in the
CFx datapath is executed in two stages. Every time a sign change is
detected in the energy accumulation at the end of the first stage,
that is, after the energy accumulated into the accumulator
reaches one of the WTHR, VARTHR, or VATHR thresholds, a
dedicated interrupt can be triggered synchronously with the
corresponding CFx pulse. The sign of each sum can be read in
the PHSIGN register.
Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and
REVPSUM1, respectively) of the STATUS0 register are set
to 1 when a sign change of the sum of powers in CF3, CF2,
or CF1 datapaths occurs. To correlate these events with the
pulses generated at the CFx pins, after a sign change occurs,
Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set
in the same moment in which a high-to-low transition at the
CF3, CF2, and CF1 pin, respectively, occurs.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN,
respectively) of the PHSIGN register are set in the same moment
with Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 and
indicate the sign of the sum of phase powers. When cleared to
0, the sum is positive. When set to 1, the sum is negative.
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the
IRQ0
pin is set low, and the
status bit is set to 1 whenever a change of sign occurs. To find
the phase that triggered the interrupt, the PHSIGN register is
read immediately after reading the STATUS0 register. Next, the
status bit is cleared, and the
IRQ0
pin is set high again by writing
to the STATUS0 register with the corresponding bit set to 1.
NO LOAD CONDITION
The no load condition is defined in metering equipment standards
as occurring when the voltage is applied to the meter and no cur-
rent flows in the current circuit. To eliminate any creep effects in
the meter, the ADE7854/ADE7858/ADE7868/ADE7878contain
three separate no load detection circuits: one related to the total
active and reactive powers (ADE7858/ADE7868/ADE7878
only), one related to the fundamental active and reactive powers
(ADE7878 only), and one related to the apparent powers.
No Load Detection Based On Total Active, Reactive
Powers
This no load condition is triggered when the absolute values of
both phase total active and reactive powers are less than or equal
to positive thresholds indicated in the respective APNOLOAD
and VARNOLOAD signed 24-bit registers. In this case, the total
active and reactive energies of that phase are not accumulated
and no CFx pulses are generated based on these energies. The
APNOLOAD register represents the positive no load level of
active power relative to PMAX, the maximum active power
obtained when full-scale voltages and currents are provided at
ADC inputs. The VARNOLOAD register represents the positive
no load level of reactive power relative to PMAX. The expres-
sion used to compute APNOLOAD signed 24-bit value is
PMAX
I
I
V
V
APNOLOAD
FS
NOLOAD
FS
n
 (47)
where:
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
computed when the ADC inputs are at full scale.
V
FS
, I
FS
are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
V
n
is the nominal rms value of phase voltage.
I
NOLOAD
is the minimum rms value of phase current the meter
starts measuring.
The VARNOLOAD register usually contains the same value as
the APNOLOAD register. When APNOLOAD and VARNOLOAD
are set to negative values, the no load detection circuit is disabled.
Note that the ADE7854 measures only the total active powers.
To ensure good functionality of the ADE7854 no-load circuit,
set the VARNOLOAD register at 0x800000.
As previously stated in the Current Waveform Gain Registers
section, the serial ports of the ADE78xx work on 32-, 16-, or
8-bit words and the DSP works on 28 bits. APNOLOAD and
VARNOLOAD 24-bit signed registers are accessed as 32-bit
registers with the four MSBs padded with 0s and sign extended
to 28 bits. See Figure 35 for details.
Bit 0 (NLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[2:0]
(NLPHASE[2:0]) in the PHNOLOAD register indicate the state
of all phases relative to a no load condition and are set simulta-
neously with Bit NLOAD in the STATUS1 register. NLPHASE[0]
indicates the state of Phase A, NLPHASE[1] indicates the state