Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 65 of 100
of Phase B, and NLPHASE[2] indicates the state of Phase C.
When Bit NLPHASE[x] is cleared to 0, it means the phase is out
of a no load condition. When set to 1, it means the phase is in a
no load condition.
An interrupt attached to Bit 0 (NLOAD) in the STATUS1
register can be enabled by setting Bit 0 in the MASK1 register.
If enabled, the
IRQ1
pin is set to low, and the status bit is set
to 1 whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the
IRQ1
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Fundamental Active and
Reactive Powers—ADE7878 Only
This no load condition (available on the ADE7878 only) is
triggered when the absolute values of both phase fundamental
active and reactive powers are less than or equal to the respective
APNOLOAD and VARNOLOAD positive thresholds. In this
case, the fundamental active and reactive energies of that phase
are not accumulated, and no CFx pulses are generated based on
these energies. APNOLOAD and VARNOLOAD are the same
no load thresholds set for the total active and reactive powers.
When APNOLOAD and VARNOLOAD are set to negative
values, this no load detection circuit is disabled.
Bit 1 (FNLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[5:3]
(FNLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and are set
simultaneously with Bit FNLOAD in the STATUS1 register.
FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]
indicates the state of Phase B, and FNLPHASE[2] indicates the
state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it
means the phase is out of the no load condition. When set to 1,
it means the phase is in a no load condition.
An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1
register can be enabled by setting Bit 1 in the MASK1 register. If
enabled, the
IRQ1
pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Then the status bit is cleared and the
IRQ1
pin is set back high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Apparent Power
This no load condition is triggered when the absolute value
of phase apparent power is less than or equal to the threshold
indicated in the VANOLOAD 24-bit signed register. In this
case, the apparent energy of that phase is not accumulated
and no CFx pulses are generated based on this energy. The
VANOLOAD register represents the positive no load level
of apparent power relative to PMAX, the maximum apparent
power obtained when full-scale voltages and currents are
provided at the ADC inputs. The expression used to compute
the VANOLOAD signed 24-bit value is
PMAX
I
I
V
V
VANOLOAD
FS
NOLOAD
FS
n
××=
(48)
where:
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous apparent
power computed when the ADC inputs are at full scale.
V
FS
, I
FS
are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
V
n
is the nominal rms value of phase voltage.
I
NOLOAD
is the minimum rms value of phase current the meter
starts measuring.
When the VANOLOAD register is set to negative values, the no
load detection circuit is disabled.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878
work on 32-, 16-, or 8-bit words and the DSP works on 28 bits.
Similar to the registers presented in Figure 35, the VANOLOAD
24-bit signed register is accessed as a 32-bit register with the
four MSBs padded with 0s and sign extended to 28 bits.
Bit 2 (VANLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[8:6]
(VANLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and they are set
simultaneously with Bit VANLOAD in the STATUS1 register:
• Bit VANLPHASE[0] indicates the state of Phase A.
• Bit VANLPHASE[1] indicates the state of Phase B.
• Bit VANLPHASE[2] indicates the state of Phase C.
When Bit VAN L PHA SE[ x ] is cleared to 0, it means the phase is
out of no load condition. When set to 1, it means the phase is in
no load condition.
An interrupt attached to Bit 2 (VANLOAD) in the STATUS1
register is enabled by setting Bit 2 in the MASK1 register. If
enabled, the
IRQ1
pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the
IRQ1
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
CHECKSUM REGISTER
The ADE7854/ADE7858/ADE7868/ADE7878 have a checksum
32-bit register, CHECKSUM, that ensures certain very important
configuration registers maintain their desired value during
Normal Power Mode PSM0.
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
and another six 8-bit reserved internal registers that always have