Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 74 of 100
Figure 93 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.
Figure 94 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
See Table 53 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 24 lists the time it takes to execute an HSDC data transfer
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
Table 24. Communication Times for Various HSDC Settings
HXFER[1:0] HGAP HSIZE
1
HCLK Communication Time (μs)
00 0 N/A 0 64
00 0 N/A 1 128
00 1 0 0 77.125
00 1 0 1 154.25
00 1 1 0 119.25
00 1 1 1 238.25
01 0 N/A 0 28
01 0 N/A 1 56
01 1 0 0 33.25
01 1 0 1 66.5
01 1 1 0 51.625
01 1 1 1 103.25
10 0 N/A 0 36
10 0 N/A 1 72
10 1 0 0 43
10 1 0 1 86
10 1 1 0 66.625
10 1 1 1 133.25
1
N/A means not applicable.
HSCL
K
HSD
HSA
0
31
0
31
0
31
0
31
IAVW (32 BITS) VAWV (32 BITS) IBWV (32 BITS) CVAR (32 BITS)
08510-066
Figure 92. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
HSCL
K
HSD
HSA
0
31
0
31
0
31
IAVW (32-BIT)
7 HCLK CYCLES
VAWV (32-BIT) IBWV (32-BIT)
7 HCLK CYCLES
0
31
CVAR (32-BIT)
08510-067
Figure 93. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0