Datasheet
Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G | Page 75 of 100
HSCLK
HSD
HSA
2431 1623 815 07
IAVW (BYTE 3)
7 HCLK CYCLES
IAWV (BYTE 2) IAWV (BYTE 1) CVAR (BYTE 0)
7 HCLK CYCLES
08510-068
Figure 94. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
QUICK SETUP AS ENERGY METER
An energy meter is usually characterized by the nominal
current I
n
, nominal voltage V
n
, nominal frequency f
n
, and the
meter constant MC.
To quickly setup t he ADE7878, execute the following steps:
1.
Select the PGA gains in the phase currents, voltages, and
neutral current channels: Bits [2:0] (PGA1), Bits [5:3]
(PGA2) and Bits [8:6] (PGA3) in the Gain register.
2.
If Rogowski coils are used, enable the digital integrators in
the phase and neutral currents: Bit 0 (INTEN) set to 1 in
CONFIG register.
3.
If f
n
=60 Hz, set Bit 14 (SELFREQ) in COMPMODE
register (ADE7878 only).
4.
Initialize WTHR1 and WTHR0 registers based on
Equation 25. Make VARTHR1 (ADE7858, ADE7868, and
ADE7878 only) and VATHR1 equal to WTHR1 and
VART H R 0 (ADE7858, ADE7868, and ADE7878 only) and
VATH R0 eq ua l to W TH R 0.
5.
Initialize CF1DEN, CF2DEN, and CF3DEN based on
Equation 26.
6.
Initialize VLEVEL (ADE7878 only) and VNOM registers
based on Equation 21 and Equation 42.
7.
Enable the data memory RAM protection by writing 0xAD
to an internal 8-bit register located at Address 0xE7FE
followed by a write of 0x80 to an internal 8-bit register
located at Address 0xE7E3.
8.
Start the DSP by setting Run=1.
9.
Read the energy registers xWATTHR, xVARHR
(ADE7858, ADE7868, and ADE7878 only), xVAHR,
xFWATTHR, and xFVARHR (ADE7878 only) to erase
their content and start energy accumulation from a known
state.
10.
Enable the CF1, CF2 and CF3 frequency converter outputs
by clearing bits 9, 10 and 11 (CF1DIS, CF2DIS, and
CF3DIS) to 0 in CFMODE register.
LAYOUT GUIDELINES
Figure 95 presents a basic schematic of the ADE7878 together
with its surrounding circuitry: decoupling capacitors at pins
VDD, AVDD, DVDD and REF
in/out
, the 16.384 MHz crystal and
its load capacitors. The rest of the pins are dependent on the
particular application and are not shown here. The ADE7854,
ADE7858 and ADE7868 have an identical approach to the
decoupling capacitors, the crystal and its load capacitors.
08510-086
C1
4.7µF
C2
0.22µF
C3
4.7µF
C4
0.22µF
C5
0.1µF
C6
10µF
U1
C7
0.1µF
17
2
3
4
7
8
9
12
13
14
15
16
18
23
22
19
27
36
38
PM0
PM1
RESET
IAP
IAN
IBP
IBN
ICP
ICN
INP
INN
VN
VAP
VBP
VCP
CLKIN
SCLK/SCL
MOSI/SDA
28
24 265
29
32
37
1
10
11
20
21
NC
ADE7878ACPZ
30
31
40
25
PAD
6
AGND
PAD
DGND
39
34
33
35
C10
4.7µF
C8
20pF
R1
5MΩ
Y1
16.384MHz
2
1
C9
20pF
AVDD
DVDD
VDD
REF
IN/OUT
CLKOUT
IRQ0
IRQ1
CF1
CF2
CF3/HSCLK
MISQ/HSD
SS/HSA
Figure 95. ADE7878 Crystal and Capacitors Connections
Figure 96 and Figure 97 present a proposed layout of a printed
circuit board (PCB) with two layers that have the components
placed only on the top of the board. Following these layout
guidelines will help in creating a low noise design with higher
immunity to EMC influences.
The VDD, AVDD, DVDD and REF
in/out
pins have each two
decoupling capacitors, one of uF order and a ceramic one of
220nF or 100nF. These ceramic capacitors need to be placed the
closest the the ADE7878 as they decouple high frequency
noises, while the uF ones need to be placed in close proximity.
The crystal load capacitors need to be placed closest to the
ADE7878, while the crystal can be placed in close proximity.