Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G| Page 86 of 100
Bit
Location Bit Mnemonic Default Value Description
3 FREHF 0
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental reactive
energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.
This bit is always 0 for
ADE7854, ADE7858, and ADE7868.
4 VAEHF 0
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
5 LENERGY 0
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
6 REVAPA 0
When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 47).
7 REVAPB 0
When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 47).
8 REVAPC 0
When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 47).
9 REVPSUM1 0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath
has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register
(see Table 47).
10 REVRPA 0
When this bit is set to 1, it indicates that the Phase A reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 4 (AVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
11 REVRPB 0
When this bit is set to 1, it indicates that the Phase B reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 5 (BVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
12 REVRPC 0
When this bit is set to 1, it indicates that the Phase C reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 6 (CVARSIGN) of the PHSIGN register (see Table 47).
This bit is
always 0 for ADE7854.
13 REVPSUM2 0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath
has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN register
(see Table 47).
14 CF1
When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin; that
is, an active low pulse has been generated. The bit is set even if the CF1 output is disabled
by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at the CF1
pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 45).
15 CF2
When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2 pin;
that is, an active low pulse has been generated. The bit is set even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
16 CF3
When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin; that
is, an active low pulse has been generated. The bit is set even if the CF3 output is disabled
by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at the CF3
pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17 DREADY 0
When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP computations
have finished.
18 REVPSUM3 0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath
has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN register
(see Table 47).
31:19 Reserved 0 0000 0000 0000 Reserved. These bits are always 0.