Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G| Page 87 of 100
Table 38. STATUS1 Register (Address 0xE503)
Bit
Location
Bit Mnemonic Default Value Description
0 NLOAD 0
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on total active and reactive powers. The phase is indicated in Bits[2:0] (NLPHASE[x]) in the
PHNOLOAD register (see Table 42).
1 FNLOAD 0
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on fundamental active and reactive powers. The phase is indicated in Bits[5:3] (FNLPHASE[x])
in PHNOLOAD register (see Table 42 in which this register is described).
This bit is always 0
for ADE7854, ADE7858, and ADE7868.
2 VANLOAD 0
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on apparent power. The phase is indicated in Bits[8:6] (VANLPHASE[x]) in the PHNOLOAD
register (see Table 42).
3
ZXTOVA
0
When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.
4 ZXTOVB 0 When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.
5 ZXTOVC 0 When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.
6
ZXTOIA
0
When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.
7 ZXTOIB 0 When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.
8 ZXTOIC 0 When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.
9
ZXVA
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A voltage.
10 ZXVB 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase B voltage.
11 ZXVC 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase C voltage.
12 ZXIA 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase A current.
13 ZXIB 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase B current.
14 ZXIC 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase C current.
15 RSTDONE 1
In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register, or a
transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the
end of the transition process and after all registers changed value to default. The
IRQ1 pin
goes low to signal this moment because this interrupt cannot be disabled.
16 SAG 0
When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated
by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
17 OI 0
When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases
indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
18 OV 0
When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases
indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
19 SEQERR 0
When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A voltage
was not followed by a negative-to-positive zero crossing on Phase B voltage but by a
negative-to-positive zero crossing on Phase C voltage.
20 MISMTCH 0
When this bit is set to 1, it indicates
ISUMLVLINWVISUM >−
, where ISUMLVL is
indicated in the ISUMLVL register. This bit is always 0 for ADE7854 and ADE7858.
21 Reserved 1 Reserved. This bit is always set to 1.
22 Reserved 0 Reserved. This bit is always set to 0.
23
PKI
0
When this bit is set to 1, it indicates that the period used to detect the peak value in the
current channel has ended. The IPEAK register contains the peak value and the phase where
the peak has been detected (see
Table 35).
24
PKV
0
When this bit is set to 1, it indicates that the period used to detect the peak value in the
voltage channel has ended. VPEAK register contains the peak value and the phase where the
peak has been detected (see Table 36).
31:25 Reserved 000 0000 Reserved. These bits are always 0.