Datasheet

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
Rev. G| Page 91 of 100
Table 43. COMPMODE Register (Address 0xE60E)
Bit
Location Bit Mnemonic Default Value Description
0 TERMSEL1[0] 1
Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1
output. Phase A is included in the CF1 outputs calculations.
1 TERMSEL1[1] 1 Phase B is included in the CF1 outputs calculations.
2 TERMSEL1[2] 1 Phase C is included in the CF1 outputs calculations.
3 TERMSEL2[0] 1
Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2
output. Phase A is included in the CF2 outputs calculations.
4 TERMSEL2[1] 1 Phase B is included in the CF2 outputs calculations.
5 TERMSEL2[2] 1 Phase C is included in the CF2 outputs calculations.
6 TERMSEL3[0] 1
Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3
output. Phase A is included in the CF3 outputs calculations.
7
TERMSEL3[1]
1
Phase B is included in the CF3 outputs calculations.
8 TERMSEL3[2] 1 Phase C is included in the CF3 outputs calculations.
10:9 ANGLESEL[1:0] 00 00: the angles between phase voltages and phase currents are measured.
01: the angles between phase voltages are measured.
10: the angles between phase currents are measured.
11: no angles are measured.
11 VNOMAEN 0 When this bit is 0, the apparent power on Phase A is computed regularly.
When this bit is 1, the apparent power on Phase A is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase A voltage input is ignored, and all
Phase A rms voltage instances are replaced by the value in the VNOM register.
12 VNOMBEN 0 When this bit is 0, the apparent power on Phase B is computed regularly.
When this bit is 1, the apparent power on Phase B is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase B voltage input is ignored, and all
Phase B rms voltage instances are replaced by the value in the VNOM register.
13 VNOMCEN 0 When this bit is 0, the apparent power on Phase C is computed regularly.
When this bit is 1, the apparent power on Phase C is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase C voltage input is ignored, and all
Phase C rms voltage instances are replaced by the value in the VNOM register.
14 SELFREQ 0
When the ADE7878 is connected to 50 Hz networks, this bit should be cleared to 0 (default
value). When the ADE7878 is connected to 60 Hz networks, this bit should be set to 1.
This
bit does not have any consequence for ADE7854, ADE7858, and ADE7868.
15 Reserved 0 This bit is 0 by default and it does not manage any functionality.
Table 44. Gain Register (Address 0xE60F)
Bit
Location
Bit Mnemonic Default Value Description
2:0 PGA1[2:0] 000 Phase currents gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave
like PGA1[2:0] = 000.
5:3 PGA2[2:0] 000 Neutral current gain selection.
000: gain = 1. These bits are always 000 for ADE7854 and ADE7858.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7868/ADE7878 behave like PGA2[2:0] =
000.