Datasheet

ADE9153A Data Sheet
Rev. 0 | Page 22 of 50
CALIBRATION TIME TO REACH ACCURACY (Seconds)
RELATIVE ACCURACY TARGET (%)
0.600
0.500
0.400
0.300
0.353
0.200
0.250
0.100
0
5.7
15.0 33.6 38.8
50 150 200
101.4 228.1
1501:1
1001:1
619:1
16519-016
Figure 41. Speed of Convergence for Autocalibration (Voltage Channel)
Based on the Potential Divider Ratio
MEASUREMENTS
Current Channel
The ADE9153A has two current channels. Channel A is optimized
for use with a shunt, and Channel B is for use with a current
transformer. The current channel datapaths for Channel A and
Channel B are shown in Figure 42 and Figure 43, respectively.
Current Channel Gain, xIGAIN
The ADE9153A provides current gain calibration registers,
AIGAIN and BIGAIN, with one register for each channel.
The current channel gain varies with xIGAIN, as shown in the
following equation:
Current Channel Gain =







27
2
1
xIGAIN
AI GAIN
HPF
REFERENCE
Σ-∆
MODULATOR
IAP
IAN
V
IN
V
IN
SINC4
LPF
4:1
ZERO-CROSSING
DETECTION
PHASE
COMP
HPFDIS
ZX_SRC_SEL
AI_WAV
TOTAL ACTIVE AND
FUNDAMENTAL REACTIVE
POWER CALCULATIONS
CURRENT PEAK
DETECTION
RMS_OC_SRC
ONE
CYCLE
RMS
RMS AND VA
CALCULATIONS
4kSPS
+1V
ANALOG INPUT RANGE
0V
–1V
V
IN
+
1/AI_PGAGAI
N
ANALOG INPUT RANGE
0V
–
1/AI_PGAGAI
N
PGA
16519-017
Figure 42. ADE9153A Current Channel A Datapath
BI GAIN
HPF
REFERENCE
Σ-∆
MODULATOR
IBP
V
IN
V
IN
IBN
SINC4 LPF 4:1
ZERO-CROSSING
DETECTION
PHASE
COMP
INTEGRATOR
HPFDIS
INTEN_BI
ZX_SRC_SEL
BI_WAV
CURRENT PEAK
DETECTION
ONE
CYCLE
RMS
RMS_OC_SRC
RMS
CALCULATIONS
4kSPS
+1.9V
ANALOG INPUT RANGE
0.9V
–0.1V
16519-018
Figure 43. ADE9153A Current Channel B Datapath
AVGAIN
HPF
REFERENCE
Σ-∆
MODULATOR
VAP
V
IN
VAN
SINC4
LPF
4:1
VOLTAGE PEAK
DETECTION
AV_WAV
ZERO-CROSSING
DETECTION
PHASE
COMP
HPFDIS
ZX_SRC_SEL
FUNDAMENTAL AND TOTAL
ACTIVE AND REACTIVE
POWER CALCULATIONS
ONE
CYCLE
RMS
RMS_OC_SRC
FUNDAMENTAL AND TOTAL
RMS, VA, THD
CALCULATIONS
4kSPS
V
IN
1.3V
ANALOG INPUT RANGE
0.8V
0.3V
16519-019
Figure 44. ADE9153A Voltage Channel Datapath
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