Datasheet
Data Sheet ADE9153A
Rev. 0 | Page 33 of 50
Address Name Description
Length
(Bits) Reset Access
0x210 BI_WAV
Instantaneous Phase B Current Channel waveform processed by
the DSP at 4 kSPS.
32 0x00000000 R
0x212 BIRMS Phase B filter-based current rms value updated at 4 kSPS. 32 0x00000000 R
0x219 BIRMS_OC
Phase B Current fast rms calculation; one cycle rms updated every
half cycle.
32 0x00000000 R
0x220 MS_ACAL_AICC Current Channel A mSure CC estimation from autocalibration. 32 0x00000000 R
0x221 MS_ACAL_AICERT Current Channel A mSure certainty of autocalibration. 32 0x00000000 R
0x222 MS_ACAL_BICC Current Channel B mSure CC estimation from autocalibration. 32 0x00000000 R
0x223 MS_ACAL_BICERT Current Channel B mSure certainty of autocalibration. 32 0x00000000 R
0x224 MS_ACAL_AVCC Voltage channel mSure CC estimation from autocalibration. 32 0x00000000 R
0x225 MS_ACAL_AVCERT Voltage channel mSure certainty of autocalibration. 32 0x00000000 R
0x240 MS_STATUS_CURRENT
The MS_STATUS_CURRENT register contains bits that reflect the
present state of the mSure system.
32 0x00000000 R
0x241 VERSION_DSP
This register indicates the version of the ADE9153B DSP after the
user writes run = 1 to start measurements.
32 0x00000000 R
0x242 VERSION_PRODUCT This register indicates the version of the product being used. 32 0x0009153A R
0x39D AWATT_ACC
Phase A accumulated total active power, updated after PWR_TIME
4 kSPS samples.
32 0x00000000 R
0x39E AWATTHR_LO
Phase A accumulated total active energy, least significant bits
(LSBs). Updated according to the settings in the EP_CFG and
EGY_TIME registers.
32 0x00000000 R
0x39F AWATTHR_HI
Phase A accumulated total active energy, most significant bits
(MSBs). Updated according to the settings in the EP_CFG and
EGY_TIME registers.
32 0x00000000 R
0x3B1 AVA_ACC
Phase A accumulated total apparent power, updated after
PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x3B2 AVAHR_LO
Phase A accumulated total apparent energy, LSBs. Updated
according to the settings in the EP_CFG and EGY_TIME registers.
32 0x00000000 R
0x3B3 AVAHR_HI
Phase A accumulated total apparent energy, MSBs. Updated
according to the settings in the EP_CFG and EGY_TIME registers.
32 0x00000000 R
0x3BB AFVAR_ACC
Phase A accumulated fundamental reactive power. Updated after
PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x3BC AFVARHR_LO
Phase A accumulated fundamental reactive energy, LSBs. Updated
according to the settings in the EP_CFG and EGY_TIME registers.
32 0x00000000 R
0x3BD AFVARHR_HI
Phase A accumulated fundamental reactive energy, MSBs. Updated
according to the settings in the EP_CFG and EGY_TIME registers.
32 0x00000000 R
0x3EB PWATT_ACC
Accumulated positive total active power from the AWATT register;
updated after PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x3EF NWATT_ACC
Accumulated negative total active power from the AWATT
register; updated after PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x3F3 PFVAR_ACC
Accumulated positive fundamental reactive power from the
AFVAR register, updated after PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x3F7 NFVAR_ACC
Accumulated negative fundamental reactive power from the
AFVAR register, updated after PWR_TIME 4 kSPS samples.
32 0x00000000 R
0x400 IPEAK Current peak register. 32 0x00000000 R
0x401 VPEAK Voltage peak register. 32 0x00000000 R
0x402 Status Tier 1 interrupt status register. 32 0x00000000 R/W
0x405 Mask Tier 1 interrupt enable register. 32 0x00000000 R/W
0x409 OI_LVL Overcurrent RMS_OC detection threshold level. 32 0x00FFFFFF R/W
0x40A OIA
Phase A overcurrent RMS_OC value. If overcurrent detection on this
channel is enabled with OIA_EN in the CONFIG3 register and
AIRMS_OC is greater than the OILVL threshold, this value is updated.
32 0x00000000 R
0x40B OIB Phase B overcurrent RMS_OC value. See the OIA description. 32 0x00000000 R
0x40E USER_PERIOD
User configured line period value used for RMS_OC when the
UPERIOD_SEL bit in the CONFIG2 register is set.
32 0x00500000 R/W
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