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ADF4001

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REV.

200 MHz Clock Generator PLL

FUNCTIONAL BLOCK DIAGRAM

13-BIT

N COUNTER

LOCK DETECT

CURRENT

SETTING 1

CPI3

CPI2

CPI1

CPI6

CPI5

CPI4

OUT

REF

CLK

DATA

CPGND

SET

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

24-BIT

INPUT REGISTER

N COUNTER

LATCH

OUT

ADF4001

MUXOUT

MUX

HIGH Z

CURRENT

SETTING 2

CHARGE

PUMP

CE AGND DGND

PHASE

FREQUENCY

DETECTOR

REFERENCE

FEATURES

200 MHz Bandwidth

2.7 V to 5.5 V Power Supply

Separate Charge Pump Supply (V

) Allows Extended

Tuning Voltage in 5 V Systems

Programmable Charge Pump Currents

3-Wire Serial Interface

Hardware and Software Power-Down Mode

Analog and Digital Lock Detect

Hardware Compatible to the ADF4110/ADF4111/

ADF4112/ADF4113

Typical Operating Current 4.5 mA

Ultralow Phase Noise

16-Lead TSSOP

20-Lead LFCSP

APPLICATIONS

Clock Generation

Low Frequency PLLs

Low Jitter Clock Source

Clock Smoothing

Frequency Translation

SONET, ATM, ADM, DSLAM, SDM

GENERAL DESCRIPTION

The ADF4001 clock generator can be used to implement clock

sources for PLLs that require very low noise, stable reference

signals. It consists of a low noise digital PFD (phase frequency

detector), a precision charge pump, a programmable reference

divider, and a programmable 13-bit N counter. In addition, the

14-bit reference counter (R counter) allows selectable REF

frequencies at the PFD input. A complete PLL (phase-locked

loop) can be implemented if the synthesizer is used with an exter-

nal loop filter and VCO (voltage controlled oscillator) or

VCXO (voltage controlled crystal oscillator). The N minimum

value of 1 allows flexibility in clock generation.

2013

781/461-3113

Summary of content (17 pages)

PAGE 1
a 200 MHz Clock Generator PLL ADF4001 FEATURES 200 MHz Bandwidth 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware Compatible to the ADF4110/ADF4111/ ADF4112/ADF4113 Typical Operating Current 4.
PAGE 2
ADF4001–SPECIFICATIONS1 (AV DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND = 0 V; RSET = 4.7 k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .
PAGE 3
ADF4001 TIMING CHARACTERISTICS (AV DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V; RSET = 4.7 k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .
PAGE 4
ADF4001 16 VP 15 DVDD 3 AGND 4 ADF4001 14 MUXOUT RFINB 5 TOP VIEW (Not to Scale) RFINA 6 CPGND AGND AGND RFINB RFINA 13 LE 12 DATA 11 CLK 10 CE 9 DGND NOTES 1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR). ADF4001 TOP VIEW (Not to Scale) 15 14 13 12 11 MUXOUT LE DATA CLK CE AVDD 6 7 AVDD REFIN 8 DGND 9 DGND 10 7 REFIN 8 1 2 3 4 5 NOTES 1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR). 2. CONNECT EXPOSED PAD TO AGND.
PAGE 5
Typical Performance Characteristics–ADF4001 10dB/DIVISION –40 0 RL = –40dBc/Hz rms NOISE = 0.229 DEGREES –50 0.229 rms –5 PHASE NOISE – dBc/Hz –60 AMPLITUDE – dBm –10 –15 TA = +85 C –20 TA = +25 C –25 –70 –80 –90 –100 –110 –120 –30 –130 TA = –40 C –140 100 –35 50 0 100 150 FREQUENCY – MHz 200 250 TPC 1. Input Sensitivity, VDD = 3.3 V, 100 pF on RFIN 1k 10k 100k FREQUENCY OFFSET FROM 200MHz CARRIER – Hz TPC 4.
PAGE 6
ADF4001 FROM N COUNTER LATCH CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. 13-BIT N COUNTER FROM RF INPUT STAGE TO PFD Figure 4.
PAGE 7
ADF4001 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow low-going pulses. DVDD ANALOG LOCK DETECT INPUT SHIFT REGISTER DIGITAL LOCK DETECT CONTROL MUX The ADF4001 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 13-bit N counter.
PAGE 8
ADF4001 LOCK DETECT PRECISION Table III. Reference Counter Latch Map RESERVED DB23 DB22 X X ANTIBACKLASH WIDTH TEST MODE BITS DB21 DB20 DB19 X LDP T2 CONTROL BITS 14-BIT REFERENCE COUNTER DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 DB3 DB2 DB1 DB0 R2 R1 C2 (0) C1 (0) X = DON’T CARE R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 .
PAGE 9
ADF4001 RESERVED CP GAIN Table IV. N Counter Latch Map DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 G1 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 X X DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X C2 (0) C1 (1) X = DON’T CARE N13 N12 N11 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 1 1 1 1 1 1 F4 (FUNCTION LATCH) FASTLOCK ENABLE CP GAIN 0 0 0 1 1 0 1 1 N3 N2 N1 N COUNTER DIVIDE RATIO .......... ......
PAGE 10
ADF4001 RESERVED POWERDOWN 2 FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET Table V.
PAGE 11
ADF4001 RESERVED POWERDOWN 2 FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET Table VI.
PAGE 12
ADF4001 FUNCTION LATCH Fastlock Mode 1 With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming the function latch. The charge pump current is switched to the contents of Current Setting 2. Counter Reset DB2 (F1) is the counter reset bit. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0.
PAGE 13
ADF4001 INITIALIZATION LATCH Counter Reset Method When C2, C1 = 1, 1, the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). Apply VDD. However, when the initialization latch is programmed, there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at a load point when the N counter data is latched, and the device will begin counting in close phase alignment.
PAGE 14
ADF4001 COHERENT CLOCK GENERATION 13MHz SYSTEM CLOCK FOR GSM R1 REFIN When testing A/D converters, it is often advantageous to use a coherent test system, that is, a system that ensures a specific relationship between the A/D converter input signal and the A/D converter sample rate. Thus, when doing an FFT on this data, there is no longer any need to apply the window weighting function.
PAGE 15
ADF4001 INTERFACING ADSP-2181 Interface The ADF4001 family has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table.
PAGE 16
ADF4001 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 13. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.
PAGE 17
ADF4001 REVISION HISTORY 4/13—Rev. A to Rev. B Changed RFINA to RFINB from ±320 mV to ±600 mV ................ 3 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 10/03—Rev. 0 to Rev. A Changes to Specifications ................................................................ 2 Edits to Ordering Guide ..................................................................