Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4007BCPZ

High Frequency Divider/PLL Synthesizer

Data Sheet

ADF4007

Rev. B

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FEATURES

7.5 GHz bandwidth

Maximum PFD frequency of 120 MHz

Divide ratios of 8, 16, 32, or 64

2.7 V to 3.3 V power supply

Separate charge pump supply (V

) allows extended tuning

voltage in 3 V systems

SET

control of charge pump current

Hardware power-down mode

APPLICATIONS

Satellite communications

Broadband wireless access

CATV

Instrumentation

Wireless LANs

GENERAL DESCRIPTION

The ADF4007 is a high frequency divider/PLL synthesizer that

can be used in a variety of communications applications. It can

operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.

It consists of a low noise digital PFD (phase frequency detector), a

precision charge pump, and a divider/prescaler. The divider/

prescaler value can be set by two external control pins to one of

four values (8, 16, 32, or 64). The reference divider is permanently

set to 2, allowing an external REF

frequency of up to 240 MHz.

A complete PLL (phase-locked loop) can be implemented if the

synthesizer is used with an external loop filter and a VCO (voltage

controlled oscillator). Its very high bandwidth means that

frequency doublers can be eliminated in many high frequency

systems, simplifying system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

REF

N2 N1

GND

R COUNTER

÷ 2

MUX

MUXOUT

CPGND

SET

PHASE

FREQUENCY

DETECTOR

REFERENCE

CHARGE

PUMP

ADF4007

N COUNTER

÷ 8, ÷ 16,

÷ 32, ÷ 64

04537-001

Figure 1.

Summary of content (16 pages)

PAGE 1
High Frequency Divider/PLL Synthesizer ADF4007 Data Sheet FEATURES GENERAL DESCRIPTION 7.5 GHz bandwidth Maximum PFD frequency of 120 MHz Divide ratios of 8, 16, 32, or 64 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems RSET control of charge pump current Hardware power-down mode The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.
PAGE 2
ADF4007 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Input Stage ................................................................................9 Applications ....................................................................................... 1 Prescaler P ......................................................................................9 General Description ...........................................
PAGE 3
Data Sheet ADF4007 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1.
PAGE 4
ADF4007 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.
PAGE 5
Data Sheet ADF4007 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 ADF4007 TOP VIEW 15 14 13 12 11 MUXOUT M1 M2 N1 N2 NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GROUND. 04537-002 AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 CPGND AGND AGND RFINB RFINA Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No.
PAGE 6
ADF4007 Data Sheet Table 5. M Truth Table Table 4. N Truth Table N2 0 0 1 1 N1 0 1 0 1 N Value 8 16 32 64 M2 0 M1 0 0 1 1 0 1 1 Rev.
PAGE 7
Data Sheet ADF4007 TYPICAL PERFORMANCE CHARACTERISTICS Table 6. S-Parameter Data for the RF Input Frequency1 0.60000 0.70000 0.80000 0.90000 1.00000 1.10000 1.20000 1.30000 1.40000 1.50000 1.60000 1.70000 1.80000 1.90000 2.00000 2.10000 2.20000 2.30000 2.40000 2.50000 2.60000 2.70000 2.80000 2.90000 3.00000 3.10000 3.20000 3.30000 3.40000 3.50000 3.60000 3.70000 3.80000 3.90000 4.00000 4.10000 4.20000 MagS11 0.87693 0.85834 0.85044 0.83494 0.81718 0.80229 0.78917 0.77598 0.75578 0.74437 0.73821 0.
PAGE 8
ADF4007 Data Sheet 0 0 VDD = 3V VP = 3V –5 REF LEVEL = –14.0dBm –10 –15 –20 TA = +85°C –25 TA = +25°C –30 –30 OUTPUT POWER (dB) RF INPUT POWER (dBm) –20 –10 TA = –40°C –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 106MHz LOOP BANDWIDTH = 1MHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5s AVERAGES = 30 –50 –60 –70 –91.0dBc/Hz 04537-007 –80 –35 –90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.
PAGE 9
Data Sheet ADF4007 THEORY OF OPERATION REFERENCE INPUT SECTION PRESCALER P The reference input stage is shown in Figure 9. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the PFD.
PAGE 10
ADF4007 Data Sheet MUXOUT PFD Polarity The output multiplexer on the ADF4007 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by the M2 and M1 pins. Figure 12 shows the MUXOUT section in block diagram form. The PFD polarity is set by the state of M2 and M1 pins as given in the Table 5. The ability to set the polarity allows the use of VCOs with either positive or negative tuning characteristics.
PAGE 11
Data Sheet ADF4007 APPLICATIONS INFORMATION FIXED HIGH FREQUENCY LOCAL OSCILLATOR Other PLL system specifications are as follows: Figure 13 shows the ADF4007 being used with the HMC358MS8G VCO from Hittite Microwave Corporation to produce a fixedfrequency LO (local oscillator), which could be used in satellite or CATV applications. In this case, the desired LO is 6.7 GHz.
PAGE 12
ADF4007 Data Sheet USING THE ADF4007 AS A DIVIDER This part is an integrated synthesizer and VCO, in this case operating over a range of 1200 MHz to 1500 MHz. With divideby-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range is 150 MHz to 187.50 MHz. In addition to its use as a standard PLL synthesizer, the ADF4007 can also be used as a high frequency counter/divider with a value of 8, 16, 32, or 64.
PAGE 13
Data Sheet ADF4007 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-6) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad to ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad.
PAGE 14
ADF4007 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 15.
PAGE 15
Data Sheet ADF4007 NOTES Rev.