Datasheet

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PLL Frequency Synthesizer

Data Sheet

ADF4107

Rev. D Document Feedback

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FEATURES

7.0 GHz bandwidth

2.7 V to 3.3 V power supply

Separate charge pump supply (V

) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANs

Base stations for wireless radio

GENERAL DESCRIPTION

The ADF4107 frequency synthesizer can be used to implement

local oscillators in the upconversion and downconversion sections

of wireless receivers and transmitters. It consists of a low noise

digital PFD (phase frequency detector), a precision charge pump, a

programmable reference divider, programmable A and B counters,

and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B

(13-bit) counters, in conjunction with the dual-modulus

prescaler (P/P + 1), implement an N divider (N = BP + A). In

addition, the 14-bit reference counter (R counter), allows

selectable REF

frequencies at the PFD input. A complete PLL

(phase-locked loop) can be implemented if the synthesizer is

used with an external loop filter and VCO (voltage controlled

oscillator). Its very high bandwidth means that frequency

doublers can be eliminated in many high frequency systems,

simplifying system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

03338-001

CLK

DAT

REF

24-BIT INPUT

OUT

AGND

DGND

14-BIT

R COUNTER

ATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

FROM

FUNCTION

LATCH

PRESCALER

P/P

+ 1

N = BP +

LOAD

13-BIT

B COUNTER

6-BIT

A COUNTER

M3 M2 M1

MUX

OUT

HIGH Z

MUXOUT

CPGND

SET

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

REFERENCE

CHARGE

PUMP

CURRENT

SETTING 1

ADF4107

CPI3 CPI2 CPI1

CPI6

CPI5 CPI4

CURRENT

SETTING 2

Figure 1.

Summary of content (20 pages)

PAGE 1
PLL Frequency Synthesizer ADF4107 Data Sheet FEATURES GENERAL DESCRIPTION 7.0 GHz bandwidth 2.7 V to 3.
PAGE 2
ADF4107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump ..............................9 Applications ....................................................................................... 1 MUXOUT and Lock Detect...................................................... 10 General Description .........................................................................
PAGE 3
Data Sheet ADF4107 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1.
PAGE 4
ADF4107 Data Sheet B Version1 B Chips2 (Typ) Unit −93 −76 −83 −93 −76 −83 dBc/Hz typ dBc/Hz typ dBc/Hz typ −90/−92 −90/−92 dBc typ 6400 MHz Output14 −65/−70 −65/−70 dBc typ 6400 MHz Output15 −70/−75 −70/−75 dBc typ Parameter Phase Noise Performance12 900 MHz Output13 6400 MHz Output14 6400 MHz Output15 Spurious Signals 900 MHz Output13 Test Conditions/Comments @ VCO output @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 1 MHz PFD freque
PAGE 5
Data Sheet ADF4107 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3.
PAGE 6
ADF4107 Data Sheet 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VP 16 CP 2 15 DVDD CPGND 3 14 MUXOUT ADF4107 CPGND AGND AGND RFINB RFINA TOP VIEW 13 LE (Not to Scale) 12 DATA RFINB 5 11 CLK AVDD 7 10 CE REFIN 8 9 DGND NOTES: 1. TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). TOP VIEW (Not to Scale) 15 14 13 12 11 MUXOUT LE DATA CLK CE NOTES 1. TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). 2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
PAGE 7
Data Sheet ADF4107 TYPICAL PERFORMANCE CHARACTERISTICS –40 10dB/DIV RL = –40dBc/Hz RMS NOISE = 0.36° –50 PHASE NOISE (dBc/Hz) –60 –70 –80 –90 –100 –110 03338-008 –120 03338-005 –130 –140 100Hz Figure 5. Parameter Data for the RF Input Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz) 0 0 VDD = 3V VP = 3V REF LEVEL = –14.0dBm –10 –5 OUTPUT POWER (dB) –20 –10 –15 –20 TA = +85°C –30 –40 –50 –60 –70 –91.
PAGE 8
ADF4107 Data Sheet –40 –5 10dB/DIV RL = –40dBc/Hz RMS NOISE = 1.
PAGE 9
Data Sheet ADF4107 FUNCTIONAL DESCRIPTION REFERENCE INPUT STAGE A AND B COUNTERS The reference input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter.
PAGE 10
ADF4107 Data Sheet DVDD VP CHARGE PUMP HI D1 Q1 UP ANALOG LOCK DETECT U1 R DIVIDER DIGITAL LOCK DETECT CLR1 R COUNTER OUTPUT MUX CONTROL MUXOUT PROGRAMMABLE DELAY N COUNTER OUTPUT U3 CP SDOUT HI ABP1 DGND CLR2 DOWN D2 Q2 03338-021 ABP2 Figure 21. MUXOUT Circuit 03338-020 U2 N DIVIDER CPGND Figure 20. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4107 allows the user to access various internal points on the chip.
PAGE 11
Data Sheet ADF4107 LATCH SUMMARY LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
PAGE 12
ADF4107 Data Sheet LOCK DETECT PRECISION REFERENCE COUNTER LATCH MAP RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 LDP 0 T2 T1 ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R12 R13 R11 R10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R9 X = DON’T CARE ABP2 0 0 1 1 ABP1 0 1 0 1 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . .
PAGE 13
Data Sheet ADF4107 CP GAIN AB COUNTER LATCH MAP RESERVED CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 DB1 DB0 C2 (0) C1 (1) X = DON’T CARE B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... ........
PAGE 14
ADF4107 Data Sheet FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI2 CPI3 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1
PAGE 15
Data Sheet ADF4107 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
PAGE 16
ADF4107 Data Sheet FUNCTION LATCH Fastlock Mode Bit The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 25 shows the input data format for programming the function latch. DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected.
PAGE 17
Data Sheet ADF4107 Charge Pump Currents 5. Then do an AB load (01 in two LSBs). CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 25. 6. When the initialization latch is loaded, the following occurs: a. b. The function latch contents are loaded. An internal pulse resets the R, AB, and timeout counters to load-state conditions and also three-states the charge pump.
PAGE 18
ADF4107 Data Sheet APPLICATIONS Other PLL system specifications are: LOCAL OSCILLATOR FOR LMDS BASE STATION TRANSMITTER KD = 5.0 mA KV = 80 MHz/V Loop bandwidth = 70 kHz FPFD = 1 MHz N = 6300 Extra reference spur attenuation = 10 dB Figure 27 shows the ADF4107 being used with a VCO to produce the LO for an LMDS base station. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω.
PAGE 19
Data Sheet ADF4107 INTERFACING ADSP-2181 Interface The ADF4107 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table.
PAGE 20
ADF4107 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 0.65 0.60 0.55 TOP VIEW 0.80 0.75 0.70 5 10 0.