Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4108BCPZ

PLL Frequency Synthesizer

Data Sheet

ADF4108

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

8.0 GHz bandwidth

3.2 V to 3.6 V power supply

Separate charge pump supply (V

) allows extended tuning

voltage in 3.3 V systems

Programmable, dual-modulus prescaler

8/9, 16/17, 32/33, or 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

Loop filter design possible with ADIsimPLL

4 mm × 4 mm, 20-lead chip scale package

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANs

Base stations for wireless radio

GENERAL DESCRIPTION

The ADF4108 frequency synthesizer can be used to implement

local oscillators in the upconversion and downconversion sections

of wireless receivers and transmitters. It consists of a low noise

digital PFD (phase frequency detector), a precision charge pump, a

programmable reference divider, programmable A and B counters,

and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B

(13-bit) counters, in conjunction with the dual-modulus prescaler

(P/P + 1), implement an N divider (N = BP + A). In addition,

the 14-bit reference counter (R counter), allows selectable REF

frequencies at the PFD input. A complete phase-locked loop (PLL)

can be implemented if the synthesizer is used with an external

loop filter and voltage controlled oscillator (VCO). Its very high

bandwidth means that frequency doublers can be eliminated in

many high frequency systems, simplifying system architecture

and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

CLK

DATA

REF

24-BIT INPUT

OUT

AGND

DGND

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

FROM

FUNCTION

LATCH

PRESCALER

P/P + 1

N = BP + A

LOAD

13-BIT

B COUNTER

6-BIT

A COUNTER

M3 M2 M1

MUX

OUT

HIGH-Z

MUXOUT

CPGND

SET

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

REFERENCE

CHARGE

PUMP

CURRENT

SETTING 1

ADF4108

CPI3 CPI2 CPI1

CPI6 CPI5 CPI4

CURRENT

SETTING 2

06015-001

Figure 1.

Summary of content (20 pages)

PAGE 1
PLL Frequency Synthesizer ADF4108 Data Sheet FEATURES GENERAL DESCRIPTION 8.0 GHz bandwidth 3.2 V to 3.6 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3.
PAGE 2
ADF4108 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump........................ 10 Applications ....................................................................................... 1 MUXOUT and Lock Detect...................................................... 10 General Description .........................................................................
PAGE 3
Data Sheet ADF4108 SPECIFICATIONS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
ADF4108 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 9 Normalized 1/f Noise (PN1_f) 10 Phase Noise Performance 11 7900 MHz Output 12 Spurious Signals 7900 MHz Output12 Data Sheet B Version 1 B Chips 2 (Typ) Unit Test Conditions/Comments −223 −223 dBc/Hz typ PLL loop B/W = 500 kHz, measured at 100 kHz offset −122 −122 dBc/Hz typ −81 −81 dBc/Hz typ 10 kHz offset; normalized to 1 GHz @ VCO output @ 1 kHz offset and 1 MHz PFD frequency −82 −82 dBc typ @ 1 MHz offset
PAGE 5
Data Sheet ADF4108 TIMING CHARACTERISTICS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 t1 t2 t3 t4 t5 t6 2 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design but not production tested.
PAGE 6
ADF4108 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature (60 sec) Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.
PAGE 7
Data Sheet ADF4108 16 DVDD 17 DVDD 19 RSET 20 CP 18 VP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CPGND 1 15 MUXOUT AGND 2 13 DATA TOP VIEW (Not to Scale) 12 CLK 11 CE DGND 10 DGND 9 REFIN 8 AVDD 7 AVDD 6 RFINA 5 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 06015-003 RFINB 4 14 LE ADF4108 AGND 3 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4108 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS ANGS11 –17.2820 –20.6919 –24.5386 –27.3228 –31.0698 –34.8623 –38.5574 –41.9093 –45.6990 –49.4185 –52.8898 –56.2923 –60.2584 –63.1446 –65.6464 –68.0742 –71.3530 –75.5658 –79.6404 –82.8246 –85.2795 –85.6298 –86.1854 –86.4997 –88.8080 –91.9737 –95.4087 –99.1282 –102.748 –107.167 –111.883 –117.548 –123.856 –130.399 –136.744 –142.766 –149.269 –154.884 Freq 4.30000 4.40000 4.50000 4.60000 4.70000 4.80000 4.90000 5.00000 5.10000 5.20000 5.30000 5.40000 5.
PAGE 9
Data Sheet ADF4108 THEORY OF OPERATION REFERENCE INPUT STAGE A AND B COUNTERS The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter.
PAGE 10
ADF4108 Data Sheet PHASE FREQUENCY DETECTOR AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 13 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs.
PAGE 11
Data Sheet ADF4108 LATCH SUMMARY LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
PAGE 12
ADF4108 Data Sheet LOCK DETECT PRECISION REFERENCE COUNTER LATCH MAP RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) X = DON’T CARE R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . .......... .
PAGE 13
Data Sheet ADF4108 CP GAIN AB COUNTER LATCH MAP RESERVED CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 DB1 DB0 C2 (0) C1 (1) X = DON’T CARE B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... ........
PAGE 14
ADF4108 Data Sheet FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI2 CPI3 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1
PAGE 15
Data Sheet ADF4108 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI2 CPI3 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
PAGE 16
ADF4108 Data Sheet FUNCTION LATCH Fastlock Mode 1 The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 18 shows the input data format for programming the function latch. The charge pump current is switched to the contents of Current Setting 2. Counter Reset DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0).
PAGE 17
Data Sheet ADF4108 Charge Pump Currents When the initialization latch is loaded, the following occurs: CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 18. 1. The function latch contents are loaded. 2. An internal pulse resets the R, AB, and timeout counters to load state conditions and also three-states the charge pump.
PAGE 18
ADF4108 Data Sheet INTERFACING The ADF4108 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. ADUC812 INTERFACE Figure 20 shows the interface between the ADF4108 and the ADuC812 MicroConverter®.
PAGE 19
Data Sheet ADF4108 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-6) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad.
PAGE 20
ADF4108 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 22.