Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4118BRUZ

RF PLL Frequency Synthesizers

ADF4116/ADF4117/ADF4118

Rev. D

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FEATURES

ADF4116: 550 MHz

ADF4117: 1.2 GHz

ADF4118: 3.0 GHz

2.7 V to 5.5 V power supply

Separate V

allows extended tuning voltage in 3 V systems

Y Grade: −40°C to +125°C

Dual-modulus prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33

3-wire serial interface

Digital lock detect

Power-down mode

Fastlock mode

APPLICATIONS

Base stations for wireless radio

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless handsets

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs

Communications test equipment

CATV equipment

GENERAL DESCRIPTION

The ADF411x family of frequency synthesizers can be used to

implement local oscillators (LO) in the upconversion and

downconversion sections of wireless receivers and transmitters.

They consist of a low noise digital phase frequency detector

(PFD), a precision charge pump, a programmable reference

divider, programmable A and B counters, and a dual-modulus

prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in

conjunction with the dual-modulus prescaler (P/P + 1),

implement an N divider (N = BP + A). In addition, the 14-bit

reference counter (R counter) allows selectable REF

frequencies

at the PFD input. A complete phase-locked loop (PLL) can be

implemented if the synthesizer is used with an external loop

filter and voltage controlled oscillator (VCO).

All of the on-chip registers are controlled via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

REFERENCE

N = BP + A

FUNCTION

LATCH

PRESCALER

P/P + 1

14-BIT

R COUNTER

13-BIT

B COUNTER

5-BIT

A COUNTER

21-BIT

INPUT REGISTER

R COUNTER

LATCH

A, B COUNTER

LATCH

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

M3 M2 M1

HIGH Z

MUX

MUXOUT

SWITCH

OUT

FROM

FUNCTION LATCH

DGNDAGNDCE

DATA

CLK

REF

CPGND

LOCK

DETECT

ADF4116/ADF4117/ADF4118

LOAD

00392-001

Figure 1.

Summary of content (28 pages)

PAGE 1
RF PLL Frequency Synthesizers ADF4116/ADF4117/ADF4118 FEATURES GENERAL DESCRIPTION ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz 2.7 V to 5.
PAGE 2
ADF4116/ADF4117/ADF4118 TABLE OF CONTENTS Features .............................................................................................. 1 Latch Summaries ........................................................................ 14 Applications....................................................................................... 1 Latch Maps .................................................................................. 15 General Description .................................................
PAGE 3
ADF4116/ADF4117/ADF4118 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1.
PAGE 4
ADF4116/ADF4117/ADF4118 Parameter POWER SUPPLIES AVDD DVDD VP IDD (AIDD + DIDD) 6 ADF4116 ADF4117 ADF4118 IP Low-Power Sleep Mode NOISE CHARACTERISTICS ADF4118 Normalized Phase Noise Floor 7 Phase Noise Performance 8 ADF4116 540 MHz Output 9 ADF4117 900 MHz Output 10 ADF4118 900 MHz Output10 ADF4117 836 MHz Output 11 ADF4118 1750 MHz Output 12 ADF4118 1750 MHz Output 13 ADF4118 1960 MHz Output 14 Spurious Signals ADF4116 540 MHz Output10 ADF4117 900 MHz Output10 ADF4118 900 MHz Output 10 ADF4117 836 MHz Out
PAGE 5
ADF4116/ADF4117/ADF4118 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Guaranteed by design, but not production tested. Table 2.
PAGE 6
ADF4116/ADF4117/ADF4118 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND1 VP to AVDD Digital I/O Voltage to GND1 Analog I/O Voltage to GND1 REFIN, RFINA, RFINB to GND1 RFINA to RFINB Operating Temperature Range Industrial (B Version) Extended (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.
PAGE 7
ADF4116/ADF4117/ADF4118 FLO 1 16 VP CP 2 15 DVDD CPGND 3 14 MUXOUT AGND 4 13 LE RFINB 5 12 DATA RFINA 6 11 CLK AVDD 7 10 CE REFIN 8 9 ADF4116/ ADF4117/ ADF4118 TOP VIEW (Not to Scale) DGND 00392-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4116/ADF4117/ADF4118 TYPICAL PERFORMANCE CHARACTERISTICS 10dB/DIVISION –40 FREQ- PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCEUNIT OHMS GHz S MA R 50 FREQ MagS11 AngS11 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 –2.0571 –4.4427 –6.3212 –2.1393 –12.13 –13.52 –15.746 –18.056 –19.693 –22.246 –24.336 –25.948 –28.457 –29.
PAGE 9
ADF4116/ADF4117/ADF4118 0 REFERENCE LEVEL = –4.2dBm –10 –20 0 VDD = 3V, VP = 5V ICP = 1mA –10 PFD FREQUENCY = 200kHz –20 REFERENCE LEVEL = –7.0dBm PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz RES. BANDWIDTH = 1kHz –40 VIDEO BANDWIDTH = 1kHz OUTPUT POWER (dB) SWEEP = 2.5 SECONDS –50 AVERAGES = 10 –60 –70 –90.67dBc –80 RES. BANDWIDTH = 300Hz –40 VIDEO BANDWIDTH = 300Hz SWEEP = 4.2ms –50 AVERAGES = 20 –60 –72.
PAGE 10
ADF4116/ADF4117/ADF4118 REFERENCE LEVEL = –9.3dBm –10 ICP = 1mA LOOP BANDWIDTH = 100kHz –30 RES. BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz –40 SWEEP = 1.4 SECONDS –50 AVERAGES = 4 –60 –77.3dBc –70 00392-016 –80 –90 –100 –2MHz –1MHz 2800MHz 1MHz VDD = 3V VP = 5V FIRST REFERENCE SPUR (dBc) PFD FREQUENCY = 1MHz –20 OUTPUT POWER (dB) –60 VDD = 3V, VP = 5V –70 –80 –90 –100 –40 2MHz 00392-019 0 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 16.
PAGE 11
ADF4116/ADF4117/ADF4118 1.2 –60 1.0 0.6 ICP (mA) 0.4 –80 0.2 0 –0.2 –0.4 –90 –0.6 0 20 40 60 80 –1.0 –1.2 100 0 TEMPERATURE (°C) Figure 22. ADF4118 Reference Spurs vs. Temperature (836 MHz, 30 kHz, 3 kHz) 2.5 2.0 1.5 1.0 00392-023 0.5 0 50 100 150 0.5 1.0 1.5 2.0 2.5 3.0 VCP (V) 3.5 4.0 Figure 24. Charge Pump Output Characteristics 3.0 0 00392-024 –0.8 –100 DIDD (mA) VP = 5V ICP SETTING: 1mA 0.
PAGE 12
ADF4116/ADF4117/ADF4118 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION A COUNTER AND B COUNTER The reference input stage is shown in Figure 25. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A CMOS counter and B CMOS counter combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter.
PAGE 13
ADF4116/ADF4117/ADF4118 MUXOUT AND LOCK DETECT The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 28 is a simplified schematic of the PFD. The PFD includes a fixed delay element that sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.
PAGE 14
ADF4116/ADF4117/ADF4118 LATCH SUMMARIES LOCK DETECT PRECISION REFERENCE COUNTER LATCH TEST MODE BITS CONTROL BITS 14-BIT REFERENCE COUNTER, R DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LDP T4 T3 T2 T1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) CP GAIN AB COUNTER LATCH 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
PAGE 15
ADF4116/ADF4117/ADF4118 LOCK DETECT PRECISION LATCH MAPS TEST MODE BITS CONTROL BITS 14-BIT REFERENCE COUNTER, R DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LDP T4 T3 T2 T1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R14 R13 R12 •• • •• • • • • • R3 R2 R1 DIVIDE RATIO 0 0 0 •• • • • • •• • • 0 0 1 1 0 0 0 •• • • • • •• • • 0 1 0 2 0 0 0 •• • • • • •• • • 0 1 1 3 0
PAGE 16
CP GAIN ADF4116/ADF4117/ADF4118 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1) ADF4116 ADF4117/ADF4118 A4 A3 A2 A1 A COUNTER DIVIDE RATIO X X 0 0 0 0 X X 0 0 1 1 • • • • • • • • • • • • X X 1 1 0 6 X X 1 1 1 7 A5 A4 A3 A2 A1 A COUNTER DIVIDE RATIO
PAGE 17
RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET ADF4116/ADF4117/ADF4118 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) TIMER COUNTER CONTROL RESERVED MUXOUT CONTROL COUNTER OPERATION F1 CE PIN PD2 PD1 0 X X CONTROL BITS 0 NORMAL 1 R, A, B COUNTERS HELD
PAGE 18
RESERVED POWERDOWN 2 FASTLOCK MODE RESERVED FASTLOCK ENABLE CP THREESTATE PHASE DETECTOR POLARITY POWERDOWN 1 COUNTER RESET ADF4116/ADF4117/ADF4118 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X PD2 X X X TC4 TC3 TC2 TC1 F6 X F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) TIMER COUNTER CONTROL MUXOUT CONTROL COUNTER OPERATION F1 CE PIN PD2 PD1 CONTROL BITS 0 NORMAL 1 R, A, B COUNTERS HELD IN RESET M3 M2
PAGE 19
ADF4116/ADF4117/ADF4118 FUNCTION LATCH With C2 and C1 set to 1 and 0, respectively, the on-chip function latch is programmed. Figure 33 shows the input data format for programming the function latch. CHARGE PUMP THREE-STATE COUNTER RESET FASTLOCK ENABLE BIT DB2 (F1) is the counter reset bit. When this bit is set to 1, the R counter, A counter, and B counter are reset. For normal operation, this bit should be set to 0.
PAGE 20
ADF4116/ADF4117/ADF4118 • Fastlock Mode 2 uses the values in the timer counter to determine the timeout period before reverting to normal mode operation after fastlock. Fastlock Mode 2 is chosen by setting DB11 to 1. • The user must also decide how long to keep the high current (1 mA) active before reverting to low current (250 μA). This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Figure 33.
PAGE 21
ADF4116/ADF4117/ADF4118 APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR THE GSM BASE STATION TRANSMITTER SHUTDOWN CIRCUIT Figure 35 shows the ADF4117/ADF4118 being used with a VCO to produce the LO for a GSM base station transmitter. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. A typical GSM system has a 13 MHz TCXO driving the reference input without a 50 Ω termination.
PAGE 22
ADF4116/ADF4117/ADF4118 VDD RFOUT VP 100pF 7 1000pF 1000pF FREFIN 8 51Ω* 15 16 AVDD DVDD VP CP REFIN 27kΩ 0.15nF FLO VCC 3.3kΩ 2 620pF 18Ω 100pF 18Ω VCO190-902T 18Ω 1 ADF4117/ ADF4118 10kΩ 1.5nF SPI-COMPATIBLE SERIAL BUS 14 CE LOCK MUXOUT CLK DETECT DATA 100pF LE 6 RFINA 3 DGND AGND CPGND RFINB 5 4 51Ω** 100pF 9 *TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω. **OPTIONAL MATCHING RESISTOR DEPENDING ON RFOUT FREQUENCY.
PAGE 23
ADF4116/ADF4117/ADF4118 0.1µF REFIO MODULATED DIGITAL DATA AD9761 TxDAC IOUTA IOUTB 100pF VOUT IBBP QBBP LOW-PASS FILTER QOUTB QBBP 2kΩ LOIN LOIP 100pF FOX801BH-130 100pF 18Ω REFIN SERIAL DIGITAL INTERFACE CP ADF4118 680pF 1kΩ 18pF VCO190-1960T 6.8nF RFINB 100pF 10kΩ 100pF 18Ω 18Ω RFINA 100pF 51Ω POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY. Figure 37. Direct Conversion Transmitter Solution Rev.
PAGE 24
ADF4116/ADF4117/ADF4118 The ADF411x family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that are clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. The maximum allowable serial clock rate is 20 MHz.
PAGE 25
ADF4116/ADF4117/ADF4118 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 40.
PAGE 26
ADF4116/ADF4117/ADF4118 NOTES Rev.
PAGE 27
ADF4116/ADF4117/ADF4118 NOTES Rev.
PAGE 28
ADF4116/ADF4117/ADF4118 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00392-0-4/07(D) Rev.