Datasheet

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Fractional-N Frequency Synthesizer

Data Sheet

ADF4153A

Rev. A Document Feedback

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FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate V

allows extended tuning voltage

Programmable fractional modulus

Programmable charge pump current

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin-compatible with ADF4106, ADF4110/ADF4111/

ADF4112/ADF4113, and ADF4153

Consistent RF output phase

Loop filter design possible with ADIsimPLL

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)

Wireless LANs, PMR

Communications test equipment

GENERAL DESCRIPTION

The ADF4153A is a fractional-N frequency synthesizer

that implements local oscillators in the upconversion and

downconversion sections of wireless receivers and transmit-

ters. It consists of a low noise digital phase frequency detector

(PFD), a precision charge pump, and a programmable reference

divider. A sigma-delta (Σ-Δ) based fractional interpolator

allows programmable fractional-N division. The INT, FRAC,

and MOD registers define an overall N divider (N = (INT +

(FRAC/MOD))). In addition, the 4-bit reference counter (R

counter) allows selectable REFIN frequencies at the PFD input.

A complete phase-locked loop (PLL) can be implemented if the

synthesizer is used with an external loop filter and a voltage

controlled oscillator (VCO).

A simple 3-wire interface controls all on-chip registers.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

N-COUNTER

RFCP3 RFCP2 RFCP1

REFERENCE

DATA

24-BIT

DATA

CLK

REF

AGND

DGND

DIV

DGND CPGND

SDV

SET

OUTPUT

MUX

–

HIGH-Z

PHASE

FREQUENCY

DETECTOR

ADF4153A

THIRD ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

CURRENT

SETTING

×2

DOUBLER

4-BIT

R COUNTER

CHARGE

PUMP

MUXOUT

11047-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Fractional-N Frequency Synthesizer ADF4153A Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.
PAGE 2
ADF4153A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 N Divider Register, R0 ............................................................... 15 Applications ....................................................................................... 1 R Divider Register, R1................................................................ 15 General Description ...........................................................
PAGE 3
Data Sheet ADF4153A SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1.
PAGE 4
ADF4153A Data Sheet TIMING SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2.
PAGE 5
Data Sheet ADF4153A ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 3. Parameter VDD to GND DVDD to AVDD SDVDD to AVDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +4 V −0.
PAGE 6
ADF4153A Data Sheet LE RFINB 5 TOP VIEW (Not to Scale) RFINA 12 DATA 6 11 CLK AVDD 7 10 SDVDD REFIN 8 9 DGND 15 MUXOUT CPGND 1 AGND 2 ADF4153A 14 LE AGND 3 TOP VIEW (Not to Scale) 13 DATA RFINB 4 RFINA 5 12 CLK 11 SDVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. Figure 3.
PAGE 7
Data Sheet ADF4153A TYPICAL PERFORMANCE CHARACTERISTICS Settings for single-sideband plots and phase noise vs. temperature plot: loop bandwidth = 20 kHz, reference = 100 MHz, PFD = 25 MHz, carrier frequency = 1720.2 MHz, N = 68, MOD = 125, FRAC = 101, ICP = 2.5 mA, VCO = Mini-Circuits ROS-1800+, evaluation board = EV-ADF4153ASD1Z, measurements taken on the Agilent E5052 signal source analyzer operating in phase noise mode.
PAGE 8
ADF4153A Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION RF INT DIVIDER The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed.
PAGE 9
Data Sheet ADF4153A PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The ADF4153A digital section includes a 4-bit RF R counter, a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE.
PAGE 10
ADF4153A Data Sheet REGISTER MAPS FASTLOCK N DIVIDER REG (R0) DB23 DB22 FL1 N9 DB21 DB20 N8 N7 DB19 DB18 N6 N5 DB17 N4 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) 9-BIT INTEGER VALUE (INT) DB16 DB15 DB14 N3 N2 N1 DB13 DB12 DB11 DB10 DB9 DB8 F12 F11 F10 F9 F8 F7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) DB16 DB15 R3 R2 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2
PAGE 11
ADF4153A FASTLOCK Data Sheet DB23 DB22 FL1 N9 N8 N7 DB19 DB18 N6 DB17 N5 N4 DB16 DB15 N3 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) N2 F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 0 . . . 1 0 0 1 1 . . . 0 0 1 0 1 . . . 0 0 1 2 3 . .
PAGE 12
DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD RESYNC DB19 DB18 0 M1 P1 0 1 P1 4-BIT R COUNTER DB17 DB16 DB15 DB14 R4 R2 R3 R1 PRESCALER 4/5 8/9 DB13 DB12 DB11 DB10 M12 M11 M10 M9 M12 0 0 0 . . . 1 M11 0 0 0 . . . 1 M10 0 0 0 . . . 1 1 1 1 1 DB2 M2 M1 0 1 4093 1 1 .......... 1 1 0 4094 1 1 .......... 1 1 1 4095 1 0 1 0 . . . 0 1 2 3 4 . . .
PAGE 13
POWERDOWN CP THREE-STATE COUNTER RESET DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) RESYNC DB15 DB14 DB13 S4 S3 S2 DB12 DB11 S1 U6 CP/2 REFERENCE DOUBLER LDP ADF4153A PD POLARITY Data Sheet U6 REFERENCE DOUBLER 0 1 DISABLED ENABLED S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 0 1 . . . 1 0 1 1 2 3 . . .
PAGE 14
NOISE AND SPUR MODE NOISE AND SPUR MODE Data Sheet RESERVED ADF4153A RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 T8 T7 T6 T5 0 0 0 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 RESERVED 0 RESERVED DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING 00000 11100 11111 LOW SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Figure 20. Noise and Spur Register (R3) Rev. A | Page 14 of 24 11047-020 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION.
PAGE 15
Data Sheet ADF4153A N DIVIDER REGISTER, R0 the error again exceeds 30 ns. In this case, the digital lock detect is reliable only as a loss-of-lock detector. With R0[1, 0] set to [0, 0], the on-chip N divider register is programmed. Figure 17 shows the input data format for programming this register. Prescaler (P/P + 1) 9-Bit INT Value These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor.
PAGE 16
ADF4153A Data Sheet RF Power-Down DB4 on the ADF4153A provides the programmable powerdown mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. When a power-down is activated, the following events occur: 1. All active dc current paths are removed. 2.
PAGE 17
Data Sheet ADF4153A INITIALIZATION SEQUENCE The following initialization sequence should be followed upon powering up the part: 1. Write all zeros to the noise and spur register. This ensures that all test modes are cleared. 2. Write again to the noise and spur register, this time selecting which noise and spur mode is required. For example, writing Hexadecimal 0003C7 to the part selects lowest noise mode. 3. 4. 5. 6.
PAGE 18
ADF4153A Data Sheet The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is of great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD. The modulus is programmed to 520 when in PDC mode (13 MHz/ 520 = 25 kHz).
PAGE 19
Data Sheet ADF4153A Reference Spurs When a new frequency is programmed, the second next sync pulse after the LE rising edge is used to resynchronize the output phase to the reference. The tSYNC time should be programmed to a value that is at least as long as the worst-case lock time. Doing so guarantees that the phase resync occurs after the last cycle slip in the PLL settling transient. In the example shown in Figure 22, the PFD reference is 25 MHz and MOD = 125 for a 200 kHz channel spacing.
PAGE 20
ADF4153A Data Sheet Figure 23 shows the interface between the ADF4153A and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4153A needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device.
PAGE 21
Data Sheet ADF4153A APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR A GSM BASE STATION TRANSMITTER The charge pump current is ICP = 5 mA. ADIsimPLL is used to calculate the loop filter. It is designed for a loop bandwidth of 20 kHz and a phase margin of 45 degrees. Figure 25 shows the ADF4153A being used with a VCO to produce the local oscillator (LO) for a GSM base station transmitter. The loop filter output drives the VCO, which in turn is fed back to the RF input of the PLL synthesizer.
PAGE 22
ADF4153A Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeter 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.
PAGE 23
Data Sheet ADF4153A NOTES Rev.