Datasheet

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Fractional-N Frequency Synthesizer

Data Sheet

ADF4153

Rev. F Document Feedback

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FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate V

allows extended tuning voltage

Y version available: −40°C to +125°C

Programmable fractional modulus

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113

and ADF4106

Consistent RF output phase

Loop filter design possible with ADIsimPLL

Qualified for automotive applications

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)

Wireless LANs, PMR

Communications test equipment

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer

that implements local oscillators in the upconversion

and downconversion sections of wireless receivers and

transmitters. It consists of a low noise digital phase

frequency detector (PFD), a precision charge pump, and

a programmable reference divider. There is a Σ-Δ based

fractional interpolator to allow programmable fractional-N

division. The INT, FRAC, and MOD registers define an

overall N divider (N = (INT + (FRAC/MOD))). In addition,

the 4-bit reference counter (R counter) allows selectable

REFIN frequencies at the PFD input. A complete phase-

locked loop (PLL) can be implemented if the synthesizer is

used with an external loop filter and a voltage controlled

oscillator (VCO).

A simple 3-wire interface controls all on-chip registers.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

N-COUNTER

RFCP3 RFCP2 RFCP1

REFERENCE

DATA

24-BIT

ATA

CLK

REF

AGND

DGND

DIV

DGND CPGND

SDV

SET

OUTPUT

MUX

–

HIGH-Z

PHASE

FREQUENC

DETECT

ADF4153

THIRD ORDER

FRACTIONA

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

CURRENT

SETTING

×2

DOUBLER

4-BIT

R COUNTER

CHARGE

PUMP

03685-001

MUXOUT

Figure 1.

Summary of content (24 pages)

PAGE 1
Fractional-N Frequency Synthesizer ADF4153 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.
PAGE 2
ADF4153 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 R Divider Register, R1................................................................ 16 Applications ....................................................................................... 1 Control Register, R2 ................................................................... 16 General Description ..........................................................
PAGE 3
Data Sheet ADF4153 REVISION HISTORY 11/13—Rev. E to Rev. F Change to ICP Sink/Source Parameter, Table 1 .............................. 4 Changes to Ordering Guide ...........................................................24 7/12—Rev. D to Rev. E Updated Outline Dimensions ........................................................23 Changes to Ordering Guide ...........................................................24 8/10—Rev. C to Rev. D Changes to Features Section .......................................
PAGE 4
ADF4153 Data Sheet SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1.
PAGE 5
Data Sheet ADF4153 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 5 Normalized 1/f Noise (PN1_f) 6 Phase Noise Performance 7 1750 MHz Output 8 B Version 1 Y Version 2 Unit Test Conditions/Comments −220 −220 dBc/Hz typ PLL loop BW = 500 kHz −114 −114 dBc/Hz typ −102 −102 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz @ VCO output @ 5 kHz offset, 25 MHz PFD frequency Operating temperature for B version is −40°C to +85°C.
PAGE 6
ADF4153 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 3.
PAGE 7
Data Sheet ADF4153 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 16 VP 2 15 DVDD 3 14 MUXOUT AGND 4 ADF4153 13 LE RFINB 5 TOP VIEW (Not to Scale) 12 DATA RFINA 6 11 CLK AVDD 7 10 SDVDD REFIN 8 9 DGND PIN 1 INDICATOR ADF4153 TOP VIEW (Not to Scale) 15 MUXOUT 14 LE 13 DATA 12 CLK 11 SDVDD 03685-002 AVDD AVDD REFIN DGND DGND 6 7 8 9 10 CP CPGND 1 2 3 4 5 NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
PAGE 8
ADF4153 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz, reference = 250 MHz, VCO = Sirenza 1750T VCO, evaluation board = EV-ADF4153SD1Z, measurements taken on the Agilent E5500 phase noise system. 5 –30 –40 –50 0 –5 –70 AMPLITUDE (dBm) PHASE NOISE (dBc/Hz) –60 20kHz LOOP BW, LOWEST NOISE MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.
PAGE 9
Data Sheet ADF4153 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION RF INT DIVIDER The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed.
PAGE 10
ADF4153 Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns.
PAGE 11
Data Sheet ADF4153 Table 6.
PAGE 12
ADF4153 Data Sheet FASTLOCK Table 7. N Divider Register Map (R0) 9-BIT INTEGER VALUE (INT) DB23 DB22 FL1 N9 N8 N7 DB19 DB18 N6 DB17 N5 N4 DB16 DB15 N3 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) N2 F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... ..........
PAGE 13
Data Sheet ADF4153 DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD RESYNC DB19 DB18 0 M1 P1 0 1 P1 4-BIT R COUNTER DB17 DB16 DB15 DB14 R4 R2 R3 R1 PRESCALER 4/5 8/9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M12 M11 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 M10 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... M3 0 0 1 . . . 1 M2 1 1 0 . . . 0 M1 0 1 0 . . . 0 INTERPOLATOR MODULUS VALUE (MOD) 2 3 4 . .
PAGE 14
ADF4153 Data Sheet REFERENCE DOUBLER CP/2 PD POLARITY LDP POWERDOWN CP THREE-STATE COUNTER RESET Table 9. Control Register Map (R2) CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S4 S3 S2 S1 U6 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) RESYNC CP CURRENT SETTING REFERENCE DOUBLER DISABLED ENABLED U6 0 1 S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 0 1 . . . 1 0 1 1 2 3 . . .
PAGE 15
Data Sheet ADF4153 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 10. Noise and Spur Register (R3) RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 T8 T7 T6 T5 0 0 0 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 RESERVED 0 RESERVED DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING 00000 11100 11111 LOW SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. F | Page 15 of 24 03685-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION.
PAGE 16
ADF4153 Data Sheet N DIVIDER REGISTER, R0 Prescaler (P/P + 1) With R0[1, 0] set to [0, 0], the on-chip N divider register is programmed. Table 7 shows the input data format for programming this register. The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. 9-Bit INT Value Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters.
PAGE 17
Data Sheet ADF4153 When a power-down is activated, the following events occur: NOISE AND SPUR REGISTER, R3 1. All active dc current paths are removed. 2. The synthesizer counters are forced to their load state conditions. With R3[1, 0] set to [1, 1], the on-chip noise and spur register is programmed. Table 10 shows the input data format for programming this register. 3. The charge pump is forced into three-state mode. Noise and Spur Mode 4. The digital lock detect circuitry is reset. 5.
PAGE 18
ADF4153 Data Sheet INITIALIZATION SEQUENCE The following initialization sequence should be followed upon powering up the part: 1. Write all zeros to the noise and spur register. This ensures that all test modes are cleared. 2. Write again to the noise and spur register, this time selecting which noise and spur mode is required. For example, writing Hexadecimal 0003C7 to the part selects lowest noise mode. 3. 4. 5. 6.
PAGE 19
Data Sheet ADF4153 The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is of great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD. The modulus is programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz).
PAGE 20
ADF4153 Data Sheet Reference Spurs LE SYNC (INTERNAL) PLL SETTLES TO INCORRECT PHASE The output of a fractional-N PLL can settle to any one of MOD phase offsets with respect to the input reference, where MOD is the fractional modulus. The phase resync feature in the ADF4153 can be used to produce a consistent output phase offset with respect to the input reference. This is necessary in applications where the output phase and frequency are important, such as digital beam-forming.
PAGE 21
Data Sheet ADF4153 When operating in this mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. ADSP-21xx Interface Figure 19 shows the interface between the ADF4153 and the ADSP-21xx digital signal processor. As discussed previously, the ADF4153 needs a 24-bit serial word for each latch write.
PAGE 22
ADF4153 Data Sheet APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR A GSM BASE STATION TRANSMITTER The charge pump current is ICP = 5 mA. ADIsimPLL is used to calculate the loop filter. It is designed for a loop bandwidth of 20 kHz and a phase margin of 45 degrees. Figure 20 shows the ADF4153 being used with a VCO to produce the local oscillator (LO) for a GSM base station transmitter. The loop filter output drives the VCO, which in turn is fed back to the RF input of the PLL synthesizer.
PAGE 23
Data Sheet ADF4153 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 21. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BCS SQ 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 5 10 1.00 0.85 0.
PAGE 24
ADF4153 Data Sheet ORDERING GUIDE Model 1, 2 ADF4153BRU ADF4153BRU-REEL7 ADF4153BRUZ ADF4153BRUZ-RL ADF4153BRUZ-RL7 ADF4153YRUZ ADF4153YRUZ-RL ADF4153YRUZ-RL7 ADF4153BCPZ ADF4153BCPZ-RL ADF4153BCPZ-RL7 ADF4153YCPZ ADF4153YCPZ-RL ADF4153YCPZ-RL7 ADF4153WYRUZ-RL7 EV-ADF4153SD1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +