Datasheet

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Fractional-N Frequency Synthesizer

Data Sheet

ADF4154

Rev. C

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FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate V

allows extended tuning voltage

Programmable dual-modulus prescaler 4/5, 8/9

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the ADF4110/ADF4111/

ADF4112/ADF4113, ADF4106, ADF4153

Programmable modulus on fractional-N synthesizer

Trade-off noise vs. spurious performance

Fast-lock mode with built-in timer

Loop filter design possible with ADIsimPLL™

APPLICATIONS

Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS,

CDMA, PMR, W-CDMA, supercell 3G)

Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA)

CATV equipment

Wireless LANs

Communications test equipment

GENERAL DESCRIPTION

The ADF4154 is a fractional-N frequency synthesizer that

implements local oscillators in the up conversion and down

conversion sections of wireless receivers and transmitters. It

consists of a low noise digital phase frequency detector (PFD),

a precision charge pump, and a programmable reference divider.

There is a Σ-Δ based fractional interpolator to allow programmable

fractional-N division. The INT, FRAC, and MOD registers define

an overall N-divider (N = (INT + (FRAC/MOD))). In addition,

the 4-bit reference counter (R-counter) allows selectable REF

frequencies at the PFD input. A complete phase-locked loop (PLL)

can be implemented if the synthesizer is used with an external

loop filter and a voltage-controlled oscillator (VCO).

A key feature of the ADF4154 is the fast-lock mode with a built-

in timer. The user can program a predetermined countdown

time value so that the PLL remains in wide bandwidth mode,

instead of the user having to control this time externally.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from 2.7 V to

3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

FAST-LOCK

SWITCH

N COUNTER

RFCP3

RFCP2 RFCP1

REFERENCE

DATA

24-BIT

DATA

CLOCK

REF

AGND

DGND

DIV

DGND CPGND

SDV

SET

OUTPUT

MUX

MUXOUT

–

HIGH Z

PHASE

FREQUENCY

DETECTOR

ADF4154

THIRD ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER REG

CURRENT

SETTING

×2

DOUBLER

4-BIT

R COUNTER

CHARGE

PUMP

04833-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Fractional-N Frequency Synthesizer ADF4154 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable dual-modulus prescaler 4/5, 8/9 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110/ADF4111/ ADF4112/ADF4113, ADF4106, ADF4153 Programmable modulus on fractional-N synthesizer Trade-off noise vs.
PAGE 2
ADF4154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Definitions ................................................................... 16 Applications ....................................................................................... 1 R-Divider Register, R1 ............................................................... 16 General Description ..........................................................
PAGE 3
Data Sheet ADF4154 SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Table 1.
PAGE 4
ADF4154 Data Sheet TIMING CHARACTERISTICS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design, but not production tested.
PAGE 5
Data Sheet ADF4154 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3.
PAGE 6
ADF4154 Data Sheet 16 DVDD 18 VP 17 DVDD 20 CP 19 RSET PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS 15 MUXOUT CPGND 1 15 DVDD RFINB 4 14 MUXOUT RFINA 5 10 SDVDD 9 DGND 04833-002 AVDD 7 REFIN 8 12 CLK 11 SDVDD AVDD 6 13 LE TOP VIEW RFINB 5 (Not to Scale) 12 DATA 11 CLK RFINA 6 AGND 4 13 DATA DGND 10 ADF4154 REFIN 8 CPGND 3 TOP VIEW (Not to Scale) DGND 9 CP 2 14 LE AGND 3 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
PAGE 7
Data Sheet ADF4154 TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz; reference = 250 MHz; VCO = Vari-L Company, Inc., VCO190-1750T; evaluation board = EVAL-ADF4154EB1; measurements taken with the Agilent E5500 phase noise measurement system. –130 –30 –50 PHASE NOISE (dBc/Hz) –60 PHASE NOISE (dBc/Hz) –40 20kHz LOOP BW, LOW NOISE MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.
PAGE 8
ADF4154 Data Sheet 1.700 –80 1.696 1.692 1.688 1.684 –90 FREQUENCY (GHz) –95 –100 1.680 LOCK TIME IN FAST-LOCK MODE (FAST COUNTER = 150) 1.676 1.672 1.668 LOCK TIME IN NORMAL MODE 1.664 1.660 1.656 1.652 –105 1.648 LOW SPUR MODE: 1649.7MHz TO 1686.8MHz FINAL LOOP BANDWIDTH = 60kHz –110 0 5 10 15 20 RSET VALUE (kΩ) 25 30 35 04833-013 1.
PAGE 9
Data Sheet ADF4154 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION INT, FRAC, MOD, AND R RELATIONSHIP The reference input stage is shown in Figure 14. While the device is operating, usually SW1 and SW2 are closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that the REFIN pin is not loaded while the device is powered down.
PAGE 10
ADF4154 Data Sheet MUXOUT AND LOCK DETECT Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed.
PAGE 11
Data Sheet ADF4154 REGISTERS Table 6.
PAGE 12
ADF4154 Data Sheet FAST-LOCK Table 7. N-Divider Register Map 9-BIT RF N VALUE (INT) DB23 DB22 FL1 N9 N8 N9 0 0 0 0 . . . 1 1 1 N7 N8 0 0 0 0 . . . 1 1 1 DB19 DB18 N6 N7 0 0 0 0 . . . 1 1 1 N5 DB17 N4 N6 0 1 1 1 . . . 1 1 1 DB16 DB15 N3 N2 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) F12 F11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 N5 1 0 0 0 . . . 1 1 1 N4 1 0 0 0 . . .
PAGE 13
Data Sheet ADF4154 DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD FAST LOCK TIMER DB19 DB18 M1 0 P1 0 1 P1 DB17 DB16 DB15 DB14 R4 R2 R3 R1 PRESCALER 4/5 8/9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M12 M11 M8 M7 M6 M5 M4 M3 M2 M1 M10 M9 .......... .......... .......... .......... .......... .......... .......... M1 0 1 0 . . . 0 INTERPOLATOR MODULUS VALUE (MOD) 2 3 4 . . . 4092 1 .......... 1 0 1 4093 1 ..........
PAGE 14
ADF4154 Data Sheet RF POWERDOWN RF CHARGE PUMP THREE-STATE RF COUNTER RESET DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S4 S3 S2 S1 U6 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) CHARGE PUMP CURRENT SETTING LOCK DETECT PRECISION CP/2 CONTROL BITS RESYNC PHASE DETECTOR POLARITY REFIN DOUBLER Table 9. Control Register Map REFIN DOUBLER DISABLED ENABLED U6 0 1 S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . .
PAGE 15
Data Sheet ADF4154 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 10. Noise and Spur Register RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 T9 T8 T7 T6 T5 T4 T3 T2 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 0 RESERVED RESERVED DB9, DB8, DB7, DB6, DB2 00000 11100 11111 NOISE AND SPUR SETTING LOWEST SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. C | Page 15 of 24 04833-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION.
PAGE 16
ADF4154 Data Sheet Prescaler (P/P + 1) REGISTER DEFINITIONS N-Divider Register, R0 The on-chip N-divider register is programmed by setting R0 [1, 0] to [0, 0]. Table 7 shows the input data format for programming this register. 9-Bit RF N Value (INT) These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor (see Equation 1).
PAGE 17
Data Sheet ADF4154 RF Charge Pump Three-State This bit (DB3) puts the charge pump into three-state mode when it is programmed to 1. For normal operation, it should be set to 0. RF Power-Down DB4 on the ADF4154 provides the programmable power-down mode. Setting Bit DB4 to 1 powers down the device. Setting Bit DB4 to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers.
PAGE 18
ADF4154 Data Sheet INITIALIZATION SEQUENCE The following initialization sequence should be followed after powering up the part: 1. 2. 3. 4. 5. 6. Clear all test modes by writing all 0s to the noise and spur register. Select the noise and spur mode required for the application by writing to the noise and spur register. For example, writing Hex 0003C7 to the part selects low noise mode.
PAGE 19
Data Sheet ADF4154 bandwidth can lead to notable spurious signals, which cannot be reduced significantly by the loop filter. • Using the fast-lock feature can achieve the same fast-lock time as the noise and spur register, but with the advantage of lower spurious signals because the final loop bandwidth is reduced by a quarter. Connect an extra resistor (R1A) directly from MUXOUT, as shown in Figure 19.
PAGE 20
ADF4154 Data Sheet In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum appear as broadband noise. This can degrade the in-band phase noise at the PLL output by as much as 10 dB. Therefore, for lowest noise, dither off is a better choice, particularly when the final loop BW is low enough to attenuate even the lowest frequency fractional spur.
PAGE 21
Data Sheet ADF4154 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad.
PAGE 22
ADF4154 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.
PAGE 23
Data Sheet ADF4154 NOTES Rev.
PAGE 24
ADF4154 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04833-0-8/12(C) Rev.