Datasheet

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6.2 GHz Fractional-N Frequency Synthesizer

Data Sheet

ADF4156

Rev. E Document Feedback

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FEATURES

RF bandwidth to 6.2 GHz

2.7 V to 3.3 V power supply

Separate V

pin allows extended tuning voltage

Programmable fractional modulus

Programmable charge-pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,

ADF4106, ADF4153, and ADF4154 frequency synthesizers

Programmable RF output phase

Loop filter design possible with ADIsimPLL

Cycle slip reduction for faster lock times

APPLICATIONS

CATV equipment

Base stations for mobile radio (WiMAX, GSM, PCS, DCS,

SuperCell 3G, CDMA, WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs, PMR

Communications test equipment

GENERAL DESCRIPTION

The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer

that implements local oscillators in the upconversion and down-

conversion sections of wireless receivers and transmitters. It

consists of a low noise digital phase frequency detector (PFD), a

precision charge pump, and a programmable reference divider.

There is a Σ-Δ based fractional interpolator to allow programmable

fractional-N division. The INT, FRAC, and MOD registers define

an overall N divider (N = (INT + (FRAC/MOD))). The RF output

phase is programmable for applications that require a particular

phase relationship between the output and the reference. The

ADF4156 also features cycle slip reduction circuitry, leading

to faster lock times without the need for modifications to the

loop filter.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from 2.7 V to

3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

N-COUNTER

RFCP3 RFCP2RFCP4 RFCP1

REFERENCE

DATA

32-BIT

DATA

CLOCK

REF

AGND

DGND

DIV

OUT

DIV

DGND CPGND

SET

OUTPUT

MUX

MUXOUT

–

HIGH Z

PHASE

FREQUENCY

DETECTOR

ADF4156

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

CURRENT

SETTING

×2

DOUBLER

5-BIT

R-COUNTER

CHARGE

PUMP

05863-001

CSR

DIVIDER

Figure 1.

Summary of content (24 pages)

PAGE 1
6.2 GHz Fractional-N Frequency Synthesizer ADF4156 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 6.2 GHz 2.7 V to 3.
PAGE 2
ADF4156 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Maps .................................................................................. 10 Applications ....................................................................................... 1 FRAC/INT Register, R0 ............................................................. 11 General Description .....................................................
PAGE 3
Data Sheet ADF4156 SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 1.
PAGE 4
ADF4156 Data Sheet TIMING SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 2.
PAGE 5
Data Sheet ADF4156 ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted. Table 3. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Maximum Junction Temperature Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.
PAGE 6
ADF4156 Data Sheet 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2 15 DVDD CPGND 3 ADF4156 14 MUXOUT AGND 4 TOP VIEW (Not to Scale) 13 LE RFINB 5 12 DATA RFINA 6 11 CLOCK AVDD 7 10 CE REFIN 8 9 DGND 1 2 3 4 5 PIN 1 INDICATOR ADF4156 TOP VIEW (Not to Scale) 15 MUXOUT 14 LE 13 DATA 12 CLOCK 11 CE NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
PAGE 7
Data Sheet ADF4156 TYPICAL PERFORMANCE CHARACTERISTICS PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 μA, phase noise measurements taken on the Agilent E5500 phase noise system. 6.00 10 5 5.95 0 CSR ON FREQUENCY (GHz) POWER (dBm) –5 –10 P = 4/5 P = 8/9 –15 –20 –25 5.90 5.85 CSR OFF 5.80 5.75 –30 –40 0 1 2 3 4 5 6 7 5.65 –100 9 8 05863-021 5.70 05863-017 –35 0 100 200 300 Figure 5. RF Input Sensitivity 500 600 700 800 900 Figure 8.
PAGE 8
ADF4156 Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION RF INT DIVIDER The reference input stage is shown in Figure 11. While the device is operating, SW1 and SW2 are usually closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that the REFIN pin is not loaded while the device is powered down. The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.
PAGE 9
Data Sheet ADF4156 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed-delay element that sets the width of the antibacklash pulse, which is typically 3 ns.
PAGE 10
ADF4156 Data Sheet REGISTER MAPS FRAC/INT REGISTER (R0) RESERVED DB31 MUXOUT CONTROL 12-BIT INTEGER VALUE (INT) CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M3 M4 0 M1 M2 N11 N12 N10 N7 N8 N9 N6 N5 N4 N3 N2 N1 F12 F11 F10 F8 F9 F6 F7 F5 F3 F4 F1 C3(0) C2(0) C1(0) F2 PHASE REGISTER (R1) CONTROL BITS 12-BIT PHASE VALUE (PHASE) 1 R
PAGE 11
Data Sheet ADF4156 FRAC/INT REGISTER, R0 12-Bit Fractional Value (FRAC) With the control bits (Bits[2:0]) of Register R0 set to 000, the on-chip FRAC/INT register is programmed. Figure 17 shows the input data format for programming this register. These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1.
PAGE 12
ADF4156 Data Sheet PHASE REGISTER, R1 See the Phase Resync section for more information. In most applications, the phase relationship between the RF signal and the reference is not important. In such applications, the phase value can be used to optimize the fractional and subfractional spur levels. See the Spur Consistency and Fractional Spur Optimization section for more information. With the control bits (Bits[2:0]) of Register R1 set to 001, the on-chip phase register is programmed.
PAGE 13
Data Sheet ADF4156 MOD/R REGISTER, R2 With the control bits (Bits[2:0]) of Register R1 set to 010, the on-chip MOD/R register is programmed. Figure 19 shows the input data format for programming this register. Noise and Spur Mode The noise modes on the ADF4156 are controlled by DB30 and DB29 in the MOD/R register. See Figure 19 for the truth table. The noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance.
PAGE 14
REFERENCE DOUBLER RDIV2 CURRENT SETTING PRESCALER NOISE MODE RESERVED Data Sheet CSR EN RESERVED ADF4156 CONTROL BITS 12-BIT MODULUS WORD 5-BIT R-COUNTER DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L2 L1 C1 U1 R5 CYCLE SLIP REDUCTION U1 REFERENCE DOUBLER 0 DISABLED 0 DISABLED 1 ENABLED1 1 ENABLED C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 R4 R3 R2 R1 M12 M12 M11 M10 M9 M8
PAGE 15
Data Sheet ADF4156 Phase Detector Polarity FUNCTION REGISTER, R3 DB6 in the ADF4156 sets the phase detector polarity. When the VCO characteristics are positive, this bit should be set to 1. When the characteristics are negative, DB6 should be set to 0. Note that the cycle slip reduction function cannot be used if the phase detector polarity is set to negative. With the control bits (Bits[2:0]) of Register R2 set to 011, the on-chip function register is programmed.
PAGE 16
ADF4156 Data Sheet CLK DIV REGISTER, R4 RESERVED BITS With the control bits (Bits[2:0]) of Register R3 set to 100, the on-chip clock divider register (R4) is programmed. Figure 21 shows the input data format for programming this register. All reserved bits should be set to 0 for normal operation.
PAGE 17
Data Sheet ADF4156 RF SYNTHESIZER: A WORKED EXAMPLE The following equation governs how the synthesizer should be programmed: RFOUT = [INT + (FRAC/MOD)] × [FPFD] (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. 12-BIT PROGRAMMABLE MODULUS Unlike most other fractional-N PLLs, the ADF4156 allows the user to program the modulus over a 12-bit range.
PAGE 18
ADF4156 Data Sheet In most cases, this method also provides faster lock times than the bandwidth switching mode method. In extreme cases, where cycle slips do not exist in the settling transient, the bandwidth switching mode can be used. Cycle Slip Reduction Mode Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared with the PFD frequency.
PAGE 19
Data Sheet ADF4156 ADF4156 In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum look like broadband noise. As a result, the in-band phase noise at the PLL output can be degraded by as much as 10 dB. Therefore, for lowest noise, keeping dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur.
PAGE 20
ADF4156 Data Sheet PHASE RESYNC LE SYNC (Internal) LAST CYCLE SLIP FREQUENCY PLL SETTLES TO INCORRECT PHASE PLL SETTLES TO CORRECT PHASE AFTER RESYNC PHASE Phase resync is enabled by setting Bits DB[20:19] in Register R4 to 10. When phase resync is enabled, an internal timer generates sync signals at intervals of tSYNC as indicated by the following formula: –100 0 100 200 300 400 500 600 TIME (µs) 700 800 900 1000 Figure 24.
PAGE 21
Data Sheet ADF4156 INTERFACING The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. The ADF4156 has a simple SPI-compatible serial interface for writing to the device. CLOCK, DATA, and LE control the data transfer.
PAGE 22
ADF4156 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.
PAGE 23
Data Sheet ADF4156 NOTES Rev.
PAGE 24
ADF4156 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05863-0-10/13(E) Rev.