Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4157BCPZ

High Resolution 6 GHz Fractional-

Frequency Synthesizer

Data Sheet

ADF4157

Rev. D

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FEATURES

RF bandwidth to 6 GHz

25-bit fixed modulus allows subhertz frequency resolution

2.7 V to 3.3 V power supply

Separate V

allows extended tuning voltage

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the following frequency synthesizers:

ADF4110/ADF4111/ADF4112/ADF4113/

ADF4106/ADF4153/ADF4154/ADF4156

Cycle slip reduction for faster lock times

APPLICATIONS

Satellite communications terminals, radar equipment

Instrumentation equipment

Personal mobile radio (PMR)

Base stations for mobile radio

Wireless handsets

GENERAL DESCRIPTION

The ADF4157 is a 6 GHz fractional-N frequency synthesizer with

a 25-bit fixed modulus, allowing subhertz frequency resolution

at 6 GHz. It consists of a low noise digital phase frequency detector

(PFD), a precision charge pump, and a programmable reference

divider. There is a Σ-Δ based fractional interpolator to allow

programmable fractional-N division. The INT and FRAC values

define an overall N divider, N = INT + (FRAC/2

). The ADF4157

features cycle slip reduction circuitry, which leads to faster lock

times without the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from 2.7 V to

3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

N COUNTER

RFCP3 RFCP2RFCP4 RFCP1

REFERENCE

DATA

32-BIT

DATA

CLK

REF

AGND

DGND

DIV

OUT

DIV

DGND CPGND

SET

OUTPUT

MUX

MUXOUT

–

HIGH Z

PHASE

FREQUENCY

DETECTOR

ADF4157

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

FRACTION

REG

INTEGER

REG

CURRENT

SETTING

×2

DOUBLER

5-BIT

R COUNTER

CHARGE

PUMP

CSR

÷2

DIVIDER

05874-001

Figure 1.

Summary of content (24 pages)

PAGE 1
High Resolution 6 GHz Fractional-N Frequency Synthesizer ADF4157 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 6 GHz 25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.
PAGE 2
ADF4157 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Program Modes .......................................................................... 10 Applications ....................................................................................... 1 Register Maps .................................................................................. 11 General Description ................................................
PAGE 3
Data Sheet ADF4157 SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1.
PAGE 4
ADF4157 Data Sheet TIMING SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2.
PAGE 5
Data Sheet ADF4157 ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted. Table 3. Parameter AVDD/DVDD to AGND/DGND AVDD to DVDD VP to AGND/DGND VP to AVDD/DVDD Digital I/O Voltage to AGND/DGND Analog I/O Voltage to AGND/DGND REFIN, RFINx to AGND/DGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature THERMAL RESISTANCE Rating −0.
PAGE 6
ADF4157 Data Sheet 16 DVDD 19 RSET 18 VP 17 DVDD 20 CP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 15 MUXOUT CPGND 1 AGND 2 ADF4157 TOP VIEW (Not to Scale) 2 15 DVDD RFINB 4 CPGND 3 ADF4157 14 MUXOUT RFINA 5 AGND 4 TOP VIEW (Not to Scale) 13 LE RFINB 5 12 DATA RFINA 6 11 CLK AVDD 7 10 CE REFIN 8 9 12 CLK 11 CE NOTES 1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
PAGE 7
Data Sheet ADF4157 TSSOP Pin No. 15 LFCSP Pin No. 16, 17 Mnemonic DVDD 16 18 VP N/A 21 (EPAD) Exposed Pad (EPAD) Description Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.
PAGE 8
ADF4157 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 μA, phase noise measurements taken on the Agilent E5052A phase noise system. 6.00 10 5 5.95 0 CSR ON FREQUENCY (GHz) POWER (dBm) –5 –10 P = 4/5 P = 8/9 –15 –20 –25 5.90 5.85 CSR OFF 5.80 5.75 –30 –40 0 1 2 3 4 5 6 7 8 5.65 –100 9 05874-019 5.70 05874-016 –35 0 100 200 300 400 500 600 700 800 900 TIME (µs) FREQUENCY (GHz) Figure 5.
PAGE 9
Data Sheet ADF4157 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION INT, FRAC, AND R RELATIONSHIP The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are open. This ensures that there is no loading of the REFIN pin on power-down.
PAGE 10
ADF4157 Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTER The PFD takes inputs from the R counter and the N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns.
PAGE 11
Data Sheet ADF4157 REGISTER MAPS RESERVED FRAC/INT REGISTER (R0) MUXOUT CONTROL 12-BIT MSB FRACTIONAL VALUE (FRAC) 12-BIT INTEGER VALUE (INT) CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0) LSB FRAC REGISTER (R1) 13-BIT LSB FRACTIONAL VALUE (
PAGE 12
ADF4157 Data Sheet FRAC/INT REGISTER (R0) MAP in Equation 1. See the INT, FRAC, and R Relationship section for more information. With R0[2:0] set to 000, the on-chip FRAC/INT register is programmed as shown in Figure 17. 12-Bit MSB FRAC Value These 12 bits, along with Bits DB[27:15] in the LSB FRAC register (R1), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1.
PAGE 13
Data Sheet ADF4157 LSB FRAC REGISTER (R1) MAP These 13 bits are the least significant bits of the 25-bit FRAC value, and Bits DB[14:3] in the INT/FRAC register are the most significant bits. See the RF Synthesizer: A Worked Example section for more information. With R1[2:0] set to 001, the on-chip LSB FRAC register is programmed as shown in Figure 18.
PAGE 14
ADF4157 Data Sheet R DIVIDER REGISTER (R2) MAP RDIV2 With R2[2:0] set to 010, the on-chip R divider register is programmed as shown in Figure 19. Setting this bit to 1 inserts a divide-by-2 toggle flip-flop between the R counter and the PFD. This can be used to provide a 50% duty cycle signal at the PFD for use with cycle slip reduction. CSR Enable Setting this bit to 1 enables cycle slip reduction. This is a method for improving lock times.
PAGE 15
DBB REFERENCE DOUBLER DBB RDIV2 DBB PRESCALER CSR EN CURRENT SETTING RESERVED ADF4157 DBB RESERVED RESERVED Data Sheet 5-BIT R COUNTER CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 C1 0 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 CYCLE SLIP REDUCTION U1 R5 R4 R3 U1 REFERENCE DOUBLER 0 DISABLED 0 DISABLED 1 ENABLED 1 ENABLED P1 U2 R DIVIDER 0 DISABLED
PAGE 16
ADF4157 Data Sheet FUNCTION REGISTER (R3) MAP RF Power-Down With R3[2:0] set to 011, the on-chip function register is programmed as shown in Figure 20. All reserved bits should be set to 0 for normal operation. DB[5] provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software powerdown mode, the part retains all information in its registers.
PAGE 17
Data Sheet ADF4157 TEST REGISTER (R4) MAP CLK Divider Mode With R4[2:0] set to 100, the on-chip test register (R4) is programmed as shown in Figure 21. Setting Bits DB[20:19] to 01 enables switched R fastlock. Negative Bleed Current Bits DB[18:7] are used to program the clock divider, which determines for how long the loop remains in wideband mode while the switched R fastlock technique is used.
PAGE 18
ADF4157 Data Sheet APPLICATIONS INFORMATION INITIALIZATION SEQUENCE After powering up the part, this programming sequence must be followed: 1. 2. 3. 4. 5. Test register (R4) Function register (R3) R divider register (R2) LSB FRAC register (R1) FRAC/INT register (R0) note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider.
PAGE 19
Data Sheet ADF4157 FASTLOCK TIMER AND REGISTER SEQUENCES ADF4157 R2 CP VCO If the fastlock mode is used, a timer value needs to be loaded into the PLL to determine the time spent in wide bandwidth mode. When Bits DB[20:19] in Register 4 (R4) are set to 01 (switched R fastlock enable), the timer value is loaded via the 12-bit clock divider value. To use fastlock, the PLL must be written to in the following sequence: 1. 2.
PAGE 20
ADF4157 Data Sheet LOW FREQUENCY APPLICATIONS The specification on the RF input is 0.5 GHz minimum; however, RF frequencies lower than this can be used, providing the minimum slew rate specification of 400 V/µs is met. An appropriate LVDS driver can be used to square up the RF signal before it is fed back to the ADF4157 RF input. The FIN1001 from Fairchild Semiconductor is one such LVDS driver.
PAGE 21
Data Sheet ADF4157 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.65 0.60 0.55 5 10 6 0.
PAGE 22
ADF4157 Data Sheet NOTES Rev.
PAGE 23
Data Sheet ADF4157 NOTES Rev.