Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer ADF4158 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 6.1 GHz 25-bit fixed modulus allows subhertz frequency resolution Frequency and phase modulation capability Sawtooth and triangular waveforms in the frequency domain Parabolic ramp Ramp superimposed with FSK Ramp with 2 different sweep rates Ramp delay Ramp frequency readback Ramp interruption 2.7 V to 3.
ADF4158 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 R-Divider Register (R2) Map .................................................... 17 Applications ....................................................................................... 1 Function Register (R3) Map...................................................... 19 General Description ........................................................................
Data Sheet ADF4158 REVISION HISTORY 3/13—Rev. D to Rev. E Changes to Figure 7, Figure 8, Figure 9, and Figure 10 ................ 9 Changes to Figure 22 ...................................................................... 14 Changes to Negative Bleed Current Section, Readback to MUXOUT Section, and Figure 27 ................................................ 21 Changes to Figure 28 ......................................................................
ADF4158 Data Sheet SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 1.
Data Sheet ADF4158 C Version1 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)4 Normalized 1/f Noise (PN1_f)5 Phase Noise Performance6 5805 MHz Output7 Min Typ Max Unit Test Conditions/Comments −216 dBc/Hz −110 dBc/Hz −93 dBc/Hz PLL loop bandwidth = 500 kHz; measured at 100 kHz offset 100 kHz offset; normalized to 1 GHz At VCO output At 5 kHz offset, 32 MHz PFD frequency 1 Operating temperature for C version: −40°C to +125°C. AC coupling ensures AVDD/2 bias.
ADF4158 Data Sheet Table 3. Read Timing Parameter t1 t2 t3 t4 t5 Limit at TMIN to TMAX (C Version) 20 20 25 25 10 Unit ns min ns min ns min ns min ns min Test Conditions/Comments TXDATA setup time CLK setup time to DATA (on MUXOUT) CLK high duration CLK low duration CKJ to LE setup time Read Timing Diagram TXDATA t1 t3 t4 CLK t2 MUXOUT DB36 DB35 DB2 DB1 DB0 t5 08728-226 LE NOTES 1. LE SHOULD BE KEPT HIGH DURING READBACK. Figure 3. Read Timing Diagram 100µA 1.
Data Sheet ADF4158 ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = SDGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 4. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (C Version) Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +4 V −0.
ADF4158 Data Sheet 24 23 22 21 20 19 CP RSET VP SW2 SW1 DVDD PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADF4158 TOP VIEW (Not to Scale) 18 17 16 15 14 13 SDVDD MUXOUT LE DATA CLK CE NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. 08728-003 AVDD 7 AVDD 8 REFIN 9 DGND 10 SDGND 11 TXDATA 12 CPGND AGND AGND RFINB RFINA AVDD Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No.
Data Sheet ADF4158 TYPICAL PERFORMANCE CHARACTERISTICS 5.87 –40 5.86 5.85 5.84 FREQUENCY (GHz) PHASE NOISE (dBc/Hz) –60 –80 –100 –120 5.83 5.82 5.81 5.80 5.79 5.78 –140 10k 100k 1M 10M FREQUENCY OFFSET (Hz) 5.76 –0.010 08728-035 1k –0.005 0 0.005 08728-039 5.77 –160 0.010 TIME (s) Figure 6. Phase Noise at 5805 MHz, PFD = 32 MHz, Loop Bandwidth = 100 kHz Figure 9.
ADF4158 Data Sheet 0 5.8004 5.8003 –5 5.8001 POWER (dBm) FREQUENCY (GHz) 5.8002 5.8000 5.7999 –10 –15 –20 5.7998 5.7997 08728-128 –25 5.7996 0.005 0.010 –30 0.185 3.185 4.185 5.185 6.185 7.185 Figure 14. RFIN Sensitivity-Average Over Temperature and VDD 5.80010 6 5.80005 4 5.80000 2 ICP (mA) FREQUENCY (GHz) 2.185 FREQUENCY (GHz) Figure 12.
Data Sheet ADF4158 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION 25-BIT FIXED MODULUS The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The ADF4158 has a 25-bit fixed modulus.
ADF4158 Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure 19 shows a simplified schematic of the PFD. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns.
Data Sheet ADF4158 REGISTER MAPS RAMP ON FRAC/INT REGISTER (R0) MUXOUT CONTROL 12-BIT MSB FRACTIONAL VALUE (FRAC) 12-BIT INTEGER VALUE (INT) CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0) LSB FRAC REGISTER (R1) 13-BIT LSB FRACTIONAL VALUE (
ADF4158 Data Sheet LE SEL TEST REGISTER (R4) NEG BLEED CURRENT RESERVED READBACK TO MUXOUT CLK DIV MODE 12-BIT CLOCK DIVIDER VALUE CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LS1 0 0 0 0 0 0 NB2 NB1 R2 R1 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 C3(1) C2(0) C1(0) DEV SEL RAMP 2 EN FSK RAMP EN INTERRUPT PAR RAMP RESERVED TX R
Data Sheet ADF4158 FRAC/INT REGISTER (R0) MAP 12-Bit MSB Fractional Value (FRAC) With Register R0 DB[2:0] set to [0, 0, 0], the on-chip FRAC/ INT register is programmed as shown in Figure 23. These 12 bits, along with Bits DB[27:15] in the LSB FRAC register (Register R1), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 2.
ADF4158 Data Sheet LSB FRAC REGISTER (R1) MAP are the least significant bits (LSB) of the 25-bit FRAC value, and Bits DB[14:3] in the INT/FRAC register are the most significant bits (MSB). See the RF Synthesizer: A Worked Example section for more information. With Register R1 DB[2:0] set to [0, 0, 1], the on-chip LSB FRAC register is programmed as shown in Figure 24.
Data Sheet ADF4158 R-DIVIDER REGISTER (R2) MAP With Register R2 DB[2:0] set to [0, 1, 0], the on-chip R-divider register is programmed as shown in Figure 25. Reserved Bits RDIV2 Setting DB21 to 1 inserts a divide-by-2 toggle flip-flop between the R-counter and the PFD. This can be used to provide a 50% duty cycle signal at the PFD for use with cycle slip reduction. Reference Doubler All reserved bits should be set to 0 for normal operation.
DBB REFERENCE DOUBLER DBB RDIV2 DBB RESERVED CSR EN DBB CP CURRENT SETTING PRESCALER Data Sheet RESERVED ADF4158 5-BIT R COUNTER CONTROL BITS 12-BIT CLK1 DIVIDER DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 CR1 0 CR1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 CYCLE SLIP REDUCTION U1 R5 R4 R3 U1 REFERENCE DOUBLER R2 R1 D12 D11 D10 D9 D8 0 DISABLED 0 DISABLED D12 D11 1 ENABLED
Data Sheet ADF4158 FUNCTION REGISTER (R3) MAP Phase Detector (PD) Polarity With Register R3 DB[2:0] set to [0, 1, 1], the on-chip function register is programmed as shown in Figure 26. DB6 sets the phase detector polarity. When the VCO characteristics are positive, set this bit to 1. When the VCO characteristics are negative, set this bit to 0. Reserved Bits Power-Down All reserved bits should be set to 0 for normal operation.
CP THREE-STATE COUNTER RESET POWER-DOWN PD POLARITY LDP PSK EN RESERVED SD RESET N SEL RESERVED FSK EN Data Sheet RAMP MODE ADF4158 CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 NS1 0 0 0 0 0 0 0 0 0 0 0 0 NS1 U12 0 0 RM2 RM1 PE1 FE1 U11 U10 U9 U8 N SEL 0 N WORD LOAD ON SDCLK 1 N WORD LOAD DELAYED 4 CYCLES RM2 RM1 U11 U12 Σ-Δ RESET 0 ENAB
Data Sheet ADF4158 TEST REGISTER (R4) MAP Readback to MUXOUT With Register R4 DB[2:0] set to [1, 0, 0], the on-chip test register (R4) is programmed as shown in Figure 27. DB[22:21] enable or disable the readback to MUXOUT function. This function allows reading back the synthesizer’s frequency at the moment of interrupt. When using readback to MUXOUT, negative bleed current must be off. LE SEL In some applications, it is necessary to synchronize LE with the reference signal.
ADF4158 Data Sheet FSK Ramp Enable DEVIATION REGISTER (R5) MAP Setting DB25 to 1 enables the FSK ramp. Setting DB25 to 0 disables the FSK ramp. With Register R5 DB[2:0] set to [1, 0, 1], the on-chip deviation register is programmed as shown in Figure 28. Ramp 2 Enable Reserved Bits Setting DB24 to 1 enables the second ramp. Setting DB24 to 0 disables the second ramp. All reserved bits should be set to 0 for normal operation.
Data Sheet ADF4158 Step SEL With Register R6 DB[2:0] set to [1, 1, 0], the on-chip step register is programmed as shown in Figure 29. Setting DB23 to 0 chooses Step Word 1. Setting DB23 to 1 chooses Step Word 2. Reserved Bits 20-Bit Step Word All reserved bits should be set to 0 for normal operation. DB[22:3] determine the step word. Step word is a number of steps in the ramp.
ADF4158 Data Sheet DELAY REGISTER (R7) MAP Delay Clock Select With Register R7 DB[2:0] set to [1, 1, 1], the on-chip delay register is programmed as shown in Figure 30. Setting DB16 to 0 selects the PFD clock as the delay clock. Setting DB16 to 1 selects PFD × CLK1 (CLK1 set by DB[14:3] in Register R2) as delay clock. Reserved Bits Delayed Start Enable All reserved bits should be set to 0 for normal operation. Setting DB15 to 1 enables delayed start. Setting DB15 to 0 disables delayed start.
Data Sheet ADF4158 APPLICATIONS INFORMATION INITIALIZATION SEQUENCE REFERENCE DOUBLER AND REFERENCE DIVIDER After powering up the part, administer the following programming sequence: The reference doubler on chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. 1. 2. 3. 4. 5. 6. 7. 8.
ADF4158 Data Sheet WAVEFORM GENERATION The ADF4158 is capable of generating four types of waveforms in the frequency domain: single ramp burst, single sawtooth burst, sawtooth ramp, and triangular ramp. Figure 31 through Figure 34 show the types of waveforms available. Note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is negative.
Data Sheet ADF4158 Waveform Deviations and Timing Single Sawtooth Burst Figure 35 shows a version of a burst or ramp. The key parameters that define a burst or ramp are In the single sawtooth burst, the N-divide value is reset to its initial value on the next timeout interval after the number of steps has taken place. The ADF4158 retains this N-divide value. Frequency deviation Timeout interval Number of steps Sawtooth Ramp The sawtooth ramp is a repeated version of the single sawtooth burst.
ADF4158 Data Sheet To calculate the DEV word, use Equation 12. DEV = (15) Example If, for example • • 250 kH z = 20,971.52 25 MHz 4 × 2 2 25 Rounding this to 20,972 and recalculating using Equation 9 to get the actual deviation frequency, fDEV, thus produces the following: fDEV = (25 MHz/225) × (20,972 × 24) = 250.006 kHz PLL is locked to 5790 MHz and fPFD = 25MHz. Ramp 1 jumps 100 steps, each of which lasts 10 µs and has a frequency deviation of 100 kHz.
Data Sheet ADF4158 Delay Between Ramps FREQUENCY DELAY 08728-028 FSK SHIFT LFM STEP = FREQUENCY SWEEP/NUMBER OF STEPS This feature adds a delay between bursts in ramp. Figure 39 shows a delay between ramps in sawtooth mode. FREQUENCY SWEEP FREQUENCY An example of ramp with FSK on the top of it is shown in Figure 37. Eventually, the ramp must be activated as described in Activating the Ramp section. TIME Figure 39.
Data Sheet FREQUENCY FREQUENCY ADF4158 Figure 40. Parabolic Ramp The following example explains how to set up and use this function. TIME 08728-100 VOLTAGE Figure 41.
Data Sheet ADF4158 Note that DB[22:21] in Register R4 should be set to 2 and DB[30:27] in Register R0 (MUXOUT control) should be set to 15 (1111). The mechanism of how single bits are read back is shown in Figure 43. For continuous frequency readback the following sequence should be used: Register 0 write LE high Pulse on TXDATA The sequence is also shown in Figure 44.
ADF4158 Data Sheet FAST-LOCK TIMER AND REGISTER SEQUENCES FAST LOCK: LOOP FILTER TOPOLOGY If the fast-lock mode is used, a timer value needs to be loaded into the PLL to determine the time spent in wide bandwidth mode. To use fast-lock mode, an extra connection from the PLL to the loop filter is needed. The damping resistor in the loop filter must be reduced to ¼ of its value while in wide bandwidth mode.
Data Sheet ADF4158 SPUR MECHANISMS LOW FREQUENCY APPLICATIONS The fractional interpolator in the ADF4158 is a third-order Σ-Δ modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/ MOD. The various spur mechanisms possible with fractional-N synthesizers and how they affect the ADF4158 are discussed in this section. The specification on the RF input is 0.
ADF4158 Data Sheet APPLICATION OF ADF4158 IN FMCW RADAR The ADF4158 in FMCW radar is used for generating ramps (sawtooth or triangle) that are necessary for this type of radar to operate. Traditionally, the PLL was driven directly by a direct digital synthesizer (DDS) to generate the required type of waveform. (the DAC driving the VCO directly) for generating FMCW ramps, which suffered from VCO tuning characteristics nonlinearities requiring compensation.
Data Sheet ADF4158 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.65 2.50 SQ 2.45 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 04-12-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 48.
ADF4158 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08728-0-3/13(E) Rev.
