Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4159CCPZ

Direct Modulation/Fast Waveform Generating,

13 GHz, Fractional-N Frequency Synthesizer

Data Sheet

ADF4159

Rev. D Document Feedback

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FEATURES

RF bandwidth to 13 GHz

High and low speed FMCW ramp generation

25-bit fixed modulus allows subhertz frequency resolution

PFD frequencies up to 110 MHz

Normalized phase noise floor of −224 dBc/Hz

FSK and PSK functions

Sawtooth, triangular, and parabolic waveform generation

Ramp superimposed with FSK

Ramp with 2 different sweep rates

Ramp delay, frequency readback, and interrupt functions

Programmable phase control

2.7 V to 3.45 V analog power supply

1.8 V digital power supply

Programmable charge pump currents

3-wire serial interface

Digital lock detect

ESD performance: 3000 V HBM, 1000 V CDM

Qualified for automotive applications

APPLICATIONS

FMCW radars

Communications test equipment

Communications infrastructure

GENERAL DESCRIPTION

The ADF4159 is a 13 GHz, fractional-N frequency synthesizer

with modulation and both fast and slow waveform generation

capability. The part uses a 25-bit fixed modulus, allowing subhertz

frequency resolution.

The ADF4159 consists of a low noise digital phase frequency

detector (PFD), a precision charge pump, and a programmable

reference divider. The Σ-Δ-based fractional interpolator allows

programmable fractional-N division. The INT and FRAC registers

define an overall N divider as N = INT + (FRAC/2

The ADF4159 can be used to implement frequency shift keying

(FSK) and phase shift keying (PSK) modulation. Frequency sweep

modes are also available to generate various waveforms in the

frequency domain, for example, sawtooth and triangular wave-

forms. Sweeps can be set to run automatically or with each step

manually triggered by an external pulse. The ADF4159 features

cycle slip reduction circuitry, which enables faster lock times

without the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface. The

ADF4159 operates with an analog power supply in the range of

2.7 V to 3.45 V and a digital power supply in the range of 1.62 V

to 1.98 V. The device can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

DATA

32-BIT

DATA

CLK

AGND

DGND

DIV

OUT

DIV

DGND CPGND

SDV

OUTPUT

MUX

MUXOUT

–

HIGH-Z

PHASE

FREQUENCY

DETECTOR

ADF4159

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRACTION

VALUE

INTEGER

VALUE

CHARGE

PUMP

DATA

REFERENCE

SET

REF

×2

DOUBLER

5-BIT

R COUNTER

÷2

DIVIDER

MODULUS

VALUE

N COUNTER

–

SW2

SW1

SDGND

10849-001

FAST LOCK

SWITCH

CSR

Figure 1.

Summary of content (36 pages)

PAGE 1
Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer ADF4159 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 13 GHz High and low speed FMCW ramp generation 25-bit fixed modulus allows subhertz frequency resolution PFD frequencies up to 110 MHz Normalized phase noise floor of −224 dBc/Hz FSK and PSK functions Sawtooth, triangular, and parabolic waveform generation Ramp superimposed with FSK Ramp with 2 different sweep rates Ramp delay, frequency readback, and int
PAGE 2
ADF4159 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Step Register (R6) Map .............................................................. 23 Applications ....................................................................................... 1 Delay Register (R7) Map ........................................................... 24 General Description ................................................................
PAGE 3
Data Sheet ADF4159 REVISION HISTORY 11/13—Rev. C to Rev. D 6/13—Rev. A to Rev. B Change to General Description Section ......................................... 1 Moved Revision History Section ..................................................... 3 Changes to Table 1 ............................................................................ 4 Change to 25-Bit Fixed Modulus Section ....................................11 Changes to Loss of Lock (LOL) Section and Lock Detect Precision (LDP) Section ....
PAGE 4
ADF4159 Data Sheet SPECIFICATIONS AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, fPFD = 110 MHz, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 1.
PAGE 5
Data Sheet ADF4159 Parameter 1 NOISE CHARACTERISTICS Normalized Phase Noise Floor 3 Integer-N Mode Fractional-N Mode Normalized 1/f Noise (PN1_f) 4 Min Typ Phase Noise Performance 5 12,002 MHz Output 6 Max Unit −224 −217 −120 dBc/Hz dBc/Hz dBc/Hz −96 dBc/Hz Test Conditions/Comments PLL loop BW = 1 MHz FRAC = 0; see Σ-Δ Modulator Mode section Measured at 10 kHz offset, normalized to 1 GHz At VCO output At 50 kHz offset, 100 MHz PFD frequency Operating temperature: −40°C to +125°C.
PAGE 6
ADF4159 Data Sheet Table 3. Read Timing Parameter t1 1 t2 t3 t4 t5 1 Limit at TMIN to TMAX tPFD + 20 20 25 25 10 Unit ns min ns min ns min ns min ns min Description TXDATA setup time CLK setup time to data (on MUXOUT) CLK high duration CLK low duration CLK to LE setup time tPFD is the period of the PFD frequency; for example, if the PFD frequency is 50 MHz, tPFD = 20 ns. Read Timing Diagram TXDATA t1 t3 t4 CLK t2 MUXOUT DB36 DB2 DB35 DB1 DB0 t5 10849-003 LE NOTES 1.
PAGE 7
Data Sheet ADF4159 ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = SDGND = CPGND = 0 V, unless otherwise noted. Table 4. Parameter AVDD to GND DVDD to GND VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND RFIN to GND Operating Temperature Range, Industrial Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature ESD Charged Device Model Human Body Model Rating −0.3 V to +3.9 V −0.3 V to +2.4 V −0.
PAGE 8
ADF4159 Data Sheet 20 SW1 19 DVDD 22 VP 21 SW2 24 CP 23 RSET PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 SDVDD CPGND 1 AGND 2 17 MUXOUT ADF4159 RFINB 4 TOP VIEW (Not to Scale) 16 LE 15 DATA TXDATA 12 SDGND 11 REFIN 9 DGND 10 13 CE AVDD 8 14 CLK AVDD 6 AVDD 7 RFINA 5 NOTES 1. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE CONNECTED TO AGND. 10849-005 AGND 3 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet ADF4159 –40 12.06 –60 12.05 12.04 –80 FREQUENCY (GHz) PHASE NOISE (dBc/Hz) TYPICAL PERFORMANCE CHARACTERISTICS –100 –120 12.03 12.02 12.01 –140 12.00 –160 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) 11.98 12.05 12.04 12.04 FREQUENCY (GHz) 12.05 12.03 12.02 12.01 11.99 200 TIME (µs) 11.98 100 200 300 400 500 TIME (µs) 12.06 12.06 12.05 12.05 FREQUENCY (GHz) 12.04 12.03 12.02 12.01 12.04 12.03 12.02 12.01 12.
PAGE 10
ADF4159 Data Sheet 12.014 12.06 12.012 12.05 12.04 12.008 FREQUENCY (GHz) FREQUENCY (GHz) 12.010 12.03 12.02 12.006 12.004 12.002 12.000 12.01 11.998 12.00 11.996 50 100 150 200 11.994 TIME (µs) Figure 12. Fast Ramp (Triangle Ramp with Different Slopes), fPFD = 100 MHz, ICP = 2.
PAGE 11
Data Sheet ADF4159 THEORY OF OPERATION REFERENCE INPUT SECTION 25-BIT FIXED MODULUS Figure 18 shows the reference input stage. The SW1 and SW2 switches are normally closed (NC in Figure 18). The SW3 switch is normally open (NO in Figure 18). When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. In this way, no loading of the REFIN pin occurs during power-down. The ADF4159 has a 25-bit fixed modulus.
PAGE 12
ADF4159 Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTER The ADF4159 digital section includes a 5-bit R counter, a 12-bit INT counter, and a 25-bit FRAC counter. Data is clocked into the 32-bit input shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the input shift register to one of eight latches on the rising edge of LE.
PAGE 13
Data Sheet ADF4159 REGISTER MAPS RAMP ON FRAC/INT REGISTER (R0) MUXOUT CONTROL 12-BIT MSB FRACTIONAL VALUE (FRAC) 12-BIT INTEGER VALUE (INT) CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0) LSB FRAC REGISTER (R1) PHASE ADJUST DBB RESERVED
PAGE 14
ADF4159 Data Sheet Σ-Δ MODULATOR MODE CLK DIV MODE RAMP STATUS CLK DIV SEL LE SEL CLOCK REGISTER (R4) 12-BIT CLK2 DIVIDER VALUE RESERVED CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LS1 S5 S4 S3 S2 S1 R5 R4 R3 R2 R1 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 CS1 0 0 0 C3(1) C2(0) C1(0) DEV SEL DUAL RAMP FSK RAMP INTERRUPT PARABOLIC RAMP TX RAMP
PAGE 15
Data Sheet ADF4159 FRAC/INT REGISTER (R0) MAP 12-Bit Integer Value (INT) When Bits DB[2:0] are set to 000, the on-chip FRAC/INT register (Register R0) is programmed (see Figure 25). Bits DB[26:15] set the INT value, which forms part of the overall feedback division factor. For more information, see the INT, FRAC, and R Counter Relationship section. Ramp On 12-Bit MSB Fractional Value (FRAC) When Bit DB31 is set to 1, the ramp function is enabled.
PAGE 16
ADF4159 Data Sheet LSB FRAC REGISTER (R1) MAP These 13 bits are the least significant bits (LSBs) of the 25-bit FRAC value; Bits DB[14:3] in the FRAC/INT register are the most significant bits (MSBs). For more information, see the RF Synthesizer Worked Example section. When Bits DB[2:0] are set to 001, the on-chip LSB FRAC register (Register R1) is programmed (see Figure 26). Reserved Bits 12-Bit Phase Value All reserved bits must be set to 0 for normal operation.
PAGE 17
Data Sheet ADF4159 R DIVIDER REGISTER (R2) MAP When Bits DB[2:0] are set to 010, the on-chip R divider register (Register R2) is programmed (see Figure 27). Reserved Bits All reserved bits must be set to 0 for normal operation. when operating the ADF4159 at frequencies greater than 8 GHz, the prescaler must be set to 8/9.
PAGE 18
DBB REFERENCE DOUBLER DBB RESERVED RDIV2 DBB CSR DBB CP CURRENT SETTING PRESCALER Data Sheet RESERVED ADF4159 DBB 5-BIT R COUNTER CONTROL BITS 12-BIT CLK1 DIVIDER VALUE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 CR1 0 CR1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 CYCLE SLIP REDUCTION 0 DISABLED 1 ENABLED U1 R5 R4 R3 U1 REFERENCE DOUBLER R2 R1 D12 D11 D10 D9 D8 D7 0 DISABLED
PAGE 19
Data Sheet ADF4159 FUNCTION REGISTER (R3) MAP Σ-Δ Reset When Bits DB[2:0] are set to 011, the on-chip function register (Register R3) is programmed (see Figure 28). For most applications, Bit DB14 should be set to 0. When this bit is set to 0, the Σ-Δ modulator is reset on each write to Register R0. If it is not required that the Σ-Δ modulator be reset on each write to Register R0, set this bit to 1. Reserved Bits All reserved bits except Bit DB17 must be set to 0 for normal operation.
PAGE 20
ADF4159 Data Sheet CP THREE-STATE COUNTER RESET POWER-DOWN PD POLARITY LDP FSK PSK RESERVED Σ-Δ RESET RESERVED N SEL NEG BLEED CURRENT RESERVED RAMP MODE Bit DB3 is the RF counter reset bit. When this bit is set to 1, the RF synthesizer counters are held in reset. For normal operation, set this bit to 0. LOL When Bit DB4 is set to 1, the charge pump is placed into threestate mode. For normal charge pump operation, set this bit to 0.
PAGE 21
Data Sheet ADF4159 CLOCK REGISTER (R4) MAP • When Bits DB[2:0] are set to 100, the on-chip clock register (Register R4) is programmed (see Figure 29). Readback to MUXOUT option: the synthesizer frequency at the moment of interruption can be read back (see the Interrupt Modes and Frequency Readback section). Ramp complete to MUXOUT option: a logic high pulse is output on the MUXOUT pin at the end of each ramp.
PAGE 22
ADF4159 Data Sheet DEVIATION REGISTER (R5) MAP Interrupt When Bits DB[2:0] are set to 101, the on-chip deviation register (Register R5) is programmed (see Figure 30). Bits DB[27:26] determine which type of interrupt is used. This feature is used for reading back the INT and FRAC value of a ramp at a given moment in time (a rising edge on the TXDATA pin triggers the interrupt). From the INT and FRAC bits, the frequency can be obtained.
PAGE 23
Data Sheet ADF4159 Step Select When Bits DB[2:0] are set to 110, the on-chip step register (Register R6) is programmed (see Figure 31). When Bit DB23 is set to 0, Step Word 1 is selected. When Bit DB23 is set to 1, Step Word 2 is selected. Reserved Bits 20-Bit Step Word All reserved bits must be set to 0 for normal operation. Bits DB[22:3] determine the step word. The step word is the number of steps in the ramp.
PAGE 24
ADF4159 Data Sheet DELAY REGISTER (R7) MAP Fast Ramp When Bits DB[2:0] are set to 111, the on-chip delay register (Register R7) is programmed (see Figure 32). When Bit DB19 is set to 1, the triangular waveform is activated with two different slopes. This waveform can be used as an alternative to the sawtooth ramp because it mitigates the overshoot at the end of the ramp in a waveform.
PAGE 25
Data Sheet ADF4159 APPLICATIONS INFORMATION INITIALIZATION SEQUENCE REFERENCE DOUBLER After powering up the ADF4159, initialize the part by programming the registers in the following sequence: The on-chip reference doubler allows the input reference signal to be doubled. This doubling is useful for increasing the PFD comparison frequency. Doubling the PFD frequency usually improves the noise performance of the system by 3 dB.
PAGE 26
ADF4159 Data Sheet Note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (Bit DB6 in Register R3 is set to 1). It cannot be used if the phase detector polarity is negative. MODULATION The ADF4159 can operate in frequency shift keying (FSK) or phase shift keying (PSK) mode.
PAGE 27
Data Sheet ADF4159 WAVEFORM DEVIATIONS AND TIMING SINGLE SAWTOOTH BURST Figure 38 shows a version of a ramp. In the single sawtooth burst, the N divider value is reset to its initial value on the next timeout interval after the number of steps has taken place. The ADF4159 retains this N divider value. TIMER SAWTOOTH RAMP FREQUENCY fDEV 10849-033 The sawtooth ramp is a repeated version of the single sawtooth burst. The waveform is repeated until the ramp is disabled. TIME Figure 38.
PAGE 28
ADF4159 Data Sheet To calculate the DEV word, use Equation 13. DEV = OTHER WAVEFORMS (13) Dual Ramps with Different Ramp Rates The ADF4159 can be configured for two ramps with different step and deviation settings. It also allows the ramp rate to be reprogrammed while another ramp is running. 250 kH z = 20,971.
PAGE 29
Data Sheet ADF4159 Ramp Mode with Superimposed FSK Signal Delayed Start In traditional approaches, FMCW radars use either linear frequency modulation (LFM) or FSK modulation. Used separately, these modulations introduce ambiguity between measured distance and velocity, especially in multitarget situations. To overcome this issue and enable unambiguous (distance and velocity) multitarget detection, use a ramp with FSK superimposed on it.
PAGE 30
ADF4159 Data Sheet Delay Between Ramps It is also possible to activate fast lock operation for the first period of delay by setting Bit DB18 in Register R7 to 1. This feature is useful for sawtooth ramps to mitigate the frequency overshoot on the transition from one sawtooth to the next. The ADF4159 can be configured to add a delay between bursts in ramps. Figure 42, Figure 43, and Figure 44 show a delay between ramps in sawtooth, triangular, and clipped triangular mode, respectively.
PAGE 31
Data Sheet ADF4159 Program the down ramp as follows. a. Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23 in Register R5 (DEV SEL), and Bit DB23 in Register R6 (STEP SEL) to 1 for Ramp 2. Configure one of the following ramp modes: • Continuous triangular ramp (set Register R3, Bits DB[11:10] to 01). Single ramp burst (set Register R3, Bits DB[11:10] to 11). b.
PAGE 32
ADF4159 Data Sheet INTERRUPT MODES AND FREQUENCY READBACK When an interrupt takes place, the data, consisting of the INT and FRAC values, can be read back via MUXOUT. The data comprises 37 bits: 12 bits represent the INT value and 25 bits represent the FRAC value. Figure 51 shows how single bits are read back. Interrupt modes are triggered from the rising edge of TXDATA. To activate this function, set Bits DB[30:27] in Register R0 to 1111, and set Bits DB[25:21] in Register R4 to 00010.
PAGE 33
Data Sheet ADF4159 FAST LOCK MODE Fast Lock Loop Filter Topology The ADF4159 can operate in fast lock mode. In this mode, the charge pump current is boosted and additional resistors are connected to maintain the stability of the loop. To use fast lock mode, an extra connection from the PLL to the loop filter is needed. The damping resistor in the loop filter must be reduced to ¼ of its value in wide bandwidth mode.
PAGE 34
ADF4159 Data Sheet SPUR MECHANISMS Low Frequency Applications The fractional interpolator in the ADF4159 is a third-order Σ-Δ modulator with a 25-bit fixed modulus (MOD). The Σ-Δ modulator is clocked at the PFD reference rate (fPFD), which allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/CLK1. This section describes the various spur mechanisms that are possible with fractional-N synthesizers and how they affect the ADF4159. The specification of the RF input is 0.
PAGE 35
Data Sheet ADF4159 APPLICATION OF THE ADF4159 IN FMCW RADAR The PLL solution also has advantages over another method for generating FMCW ramps: a DAC driving the VCO directly; this method suffers from nonlinearities of the VCO tuning characteristics, requiring compensation. The PLL method produces highly linear ramps without the need for calibration. Figure 55 shows the application of the ADF4159 in a frequency modulated continuous wave (FMCW) radar system.
PAGE 36
ADF4159 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.20 2.10 SQ 2.00 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 06-11-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 56.