Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4218LBRUZ

ADF4217L/ADF4218L/ADF4219L

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REV. C

Dual Low Power

Frequency Synthesizers

FUNCTIONAL BLOCK DIAGRAM

N = BP + A

11(13)-BIT IF

B COUNTER

6(5)-BIT IF

A COUNTER

PRESCALER

OUTPUT

MUX

LOCK

DETECT

CHARGE

PUMP

LOCK

DETECT

CHARGE

PUMP

14(15)-BIT RF

R COUNTER

14(15)-BIT IF

R COUNTER

BUFFER

22-BIT

DATA

SDOUT

N = BP + A

11(13)-BIT RF

B COUNTER

6(5)-BIT RF

A COUNTER

PRESCALER

PHASE

COMPARATOR

PHASE

COMPARATOR

ADF4217L/

ADF4218L/

ADF4219L

ADF4219L ONLY

ADF4217L

ADF4218L

ONLY

REF

CLOCK

DATA

DGND

AGND

DGND

AGND

MUXOUT

FEATURES IN ( ) REFER TO ADF4219L

NC = NO CONNECT

FEATURES

Total I

: 7.1 mA

Bandwidth/RF 3.0 GHz

ADF4217L/ADF4218L, IF 1.1 GHz

ADF4219L, IF 1.0 GHz

2.6 V to 3.3 V Power Supply

1.8 V Logic Compatibility

Separate V

Allows Extended Tuning Voltage

Selectable Dual Modulus Prescaler

Selectable Charge Pump Currents

Charge Pump Current Matching of 1%

3-Wire Serial Interface

Power-Down Mode

APPLICATIONS

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)

Wireless LANs

Communications Test Equipment

Cable TV Tuners (CATV)

GENERAL DESCRIPTION

The ADF4217L/ADF4218L/ADF4219L are low power dual

frequency synthesizers that can be used to implement local

oscillators in the up-conversion and down-conversion sections

of wireless receivers and transmitters. They can provide the LO

for both the RF and IF sections. They consist of a low noise

digital PFD (phase frequency detector), a precision charge pump,

programmable reference divider, programmable A and B counters,

and a dual modulus prescaler (P/P + 1). The A and B counters,

in conjunction with the dual modulus prescaler

(P/P + 1),

implement an N divider (N = BP + A). In addition, the 14-bit

reference counter (R Counter) allows selectable REFIN

fre-

quencies at the PFD input. A complete PLL (phase-locked

loop) can be implemented if the synthesizers are used with an

external loop filter and VCOs (voltage controlled oscillators).

Control of all the on-chip registers is via a simple 3-wire interface

with 1.8 V compatibility. The devices operate with a power supply

ranging from 2.6 V to 3.3 V and can be powered down when

not in use.

Summary of content (24 pages)

PAGE 1
a Dual Low Power Frequency Synthesizers ADF4217L/ADF4218L/ADF4219L FEATURES Total I DD: 7.1 mA Bandwidth/RF 3.0 GHz ADF4217L/ADF4218L, IF 1.1 GHz ADF4219L, IF 1.0 GHz 2.6 V to 3.3 V Power Supply 1.
PAGE 2
ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS1 (VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
PAGE 3
ADF4217L/ADF4218L/ADF4219L Parameter BChips2 (Typical) Unit Test Conditions/Comments –171 –163 –167 –159 –171 –163 –167 –159 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ –75 –90 –77 –86 –75 –90 –77 –86 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output 1.
PAGE 4
ADF4217L/ADF4218L/ADF4219L TSSOP ␪JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W LGA ␪JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W Lead Temperature, Soldering TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
ADF4217L/ADF4218L/ADF4219L PIN CONFIGURATIONS TSSOP TSSOP VDD1 1 20 VDD2 VDD1 1 20 VP1 2 19 VP2 VP1 2 19 VP2 CPRF 3 18 CPIF CPRF 3 18 CPIF DGNDRF 4 17 DGNDIF DGNDRF 4 17 RFINA 5 16 IFINA RFINA 5 16 DGNDIF IFIN RFINB AGNDRF 6 15 IFINB 15 AGNDIF 14 AGNDIF RFINB AGNDRF 6 7 7 14 NC REFIN 8 13 LE REFIN 8 13 DGNDIF 9 12 DGNDIF 9 12 MUXOUT 10 11 DATA CLK MUXOUT 10 11 LE DATA CLK ADF4217L/ ADF4218L ADF4219L VDD2 CHIP SCALE 1 VP1 2 20
PAGE 6
ADF4217L/ADF4218L/ADF4219L PIN FUNCTION DESCRIPTIONS Mnemonic Function VDD1 Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD. Output from the RF Charge Pump.
PAGE 7
Typical Performance Characteristics–ADF4217L/ADF4218L/ADF4219L 0 0 VDD = 3V VP = 3V –5 REFERENCE LEVEL = –11.2dBm –10 –20 OUTPUT POWER – dB RF INPUT POWER – dBm –10 –15 –20 –25 TA = 25ⴗC –30 VDD = 3V, VP = 5V ICP = 4mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 10 –40 –50 –60 –78dBc –70 –30 –80 –35 –90 –100 –40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –400kHz –200kHz TPC 1. Input Sensitivity, RF Input 200kHz 400kHz TPC 4.
PAGE 8
ADF4217L/ADF4218L/ADF4219L 0 –120 OUTPUT POWER – dB –20 –30 –40 VDD = 3V VP = 5V VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS AVERAGES = 20 –130 PHASE NOISE – dBc/Hz REFERENCE LEVEL = –4.2dBm –10 –50 –60 –70 –140 –150 –160 –83dBc –80 –170 –90 –100 –400kHz –200kHz 900MHz FREQUENCY 200kHz –180 400kHz TPC 7.
PAGE 9
ADF4217L/ADF4218L/ADF4219L 6 VP = 5V ICP = 4mA 4 ICP – mA 2 0 –2 –4 –6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP – V 3.5 4.0 4.5 5.0 TPC 13. Charge Pump Output Characteristics CIRCUIT DESCRIPTION Reference Input Section Prescaler The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
PAGE 10
ADF4217L/ADF4218L/ADF4219L The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: [ MUXOUT AND LOCK DETECT The output multiplexer on the ADF4217L family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables IV and VII.
PAGE 11
ADF4217L/ADF4218L/ADF4219L Table II.
PAGE 12
ADF4217L/ADF4218L/ADF4219L Table III.
PAGE 13
ADF4217L/ADF4218L/ADF4219L Table IV. ADF4217L/ADF4218L/ADF4219L IF Reference Counter Latch Map ADF4219L ONLY IF PD POLARITY IF CP GAIN THREE-STATE CPIF IF FO IF LOCK DETECT IF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 REV. C P3 P2 P5 P1 R15 R14 R13 P1 PD POLARITY 0 1 NEGATIVE POSITIVE P5 ICP 0 1 1.0mA 4.
PAGE 14
ADF4217L/ADF4218L/ADF4219L Table V. ADF4217L/ADF4218L IF AB Counter Latch Map IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB9 B2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 B1 A5 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . .
PAGE 15
ADF4217L/ADF4218L/ADF4219L Table VI. ADF4219L IF AB Counter Latch Map IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 . 1 . 1 . 1 . 1 . 0 . 30 1 1 1 1 1 31 B11 ..........
PAGE 16
ADF4217L/ADF4218L/ADF4219L Table VII. RF Reference Counter Latch Map ADF4129L ONLY RF PD POLARITY RF CP GAIN RF FO RF LOCK DETECT THREE-STATE CPIF RF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 R15 0 1 NEGATIVE POSITIVE ICP 1.0mA 4.
PAGE 17
ADF4217L/ADF4218L/ADF4219L Table VIII. ADF4217L/ADF4218L RF AB Counter Latch Map RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB9 B2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 B1 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 . . . . . . . . . . . . . . . . .
PAGE 18
ADF4217L/ADF4218L/ADF4219L Table IX. ADF4219L RF AB Counter Latch Map RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 B4 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 . . . . . . 1 1 1 1 0 30 1 1 1 1 1 31 B12 B11 ..........
PAGE 19
ADF4217L/ADF4218L/ADF4219L PROGRAM MODES Tables IV and VII show how to set up the program modes in the ADF4217L family. The following should be noted: The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. 1. IF and RF Analog Lock Detect indicate when the PLL is in lock.
PAGE 20
ADF4217L/ADF4218L/ADF4219L RF Program Modes program the new frequency and to initiate Fastlock. To come out of Fastlock, the RF CP Gain Bit should be returned to “0” and the extra damping resistor switched out. Tables IV and VII show how to set up the RF program modes. RF Charge Pump Currents P13 sets the RF charge pump current. With P13 set to “0,” ICP is 1.0 mA. With P13 set to “1,” ICP is 4.0 mA. See Table VII.
PAGE 21
ADF4217L/ADF4218L/ADF4219L RFOUT IFOUT VP VDD VP 100pF 18⍀ 100pF 18⍀ 100pF VDD2 VDD1 450pF 1.5k⍀ VP1 3.3k⍀ 2.4pF 760pF 4.7k⍀ ADF4217L/ ADF4218L/ ADF4219L 24nF MUXOUT DGNDRF AGNDRF DGNDIF AGNDIF 10MHz TCXO VCO190-1750T 690pF 18⍀ 18⍀ LOCK DETECT 100pF RFIN IFIN REFIN 18⍀ 7.5nF 100pF 51⍀ 100pF VCC CPRF CPIF VCO190-200T 18⍀ VP2 3.3k⍀ VCC CLK DATA LE 51⍀ SPI COMPATIBLE SERIAL BUS DECOUPLING CAPACITORS (22␮F/10pF) ON VDD , VP OF THE ADF4217L/ADF4218L/ADF4219L.
PAGE 22
ADF4217L/ADF4218L/ADF4219L OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 1 6.40 BSC 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.20 0.09 0.30 COPLANARITY 0.19 0.10 SEATING PLANE 0.75 0.60 0.45 8ⴗ 0ⴗ COMPLIANT TO JEDEC STANDARDS MO-153AC 24-Leadless Chip Array CASON [LGA] (CC-24) Dimensions shown in millimeters SEATING PLANE 1.20 MAX 4.50 BSC VIEW A 3.50 BSC TOP VIEW PIN 1 INDEX AREA 1.15 0.
PAGE 23
ADF4217L/ADF4218L/ADF4219L Revision History Location Page 5/03—Data Sheet changed from REV. B to REV. C. Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to TPC 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Change to OUTLINE DIMENSIONS .
PAGE 24
–24– C02655–0–5/03(C)