Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4252BCPZ

REV. B

ADF4252

Dual Fractional-N/Integer-N

Frequency Synthesizer

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

FEATURES

3.0 GHz Fractional-N/1.2 GHz Integer-N

2.7 V to 3.3 V Power Supply

Separate V

Allows Extended Tuning Voltage to 5 V

Programmable Dual Modulus Prescaler

RF: 4/5, 8/9

IF: 8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

3-Wire Serial Interface

Digital Lock Detect

Power-Down Mode

Programmable Modulus on Fractional-N Synthesizer

Trade-Off Noise versus Spurious Performance

APPLICATIONS

Base Stations for Mobile Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs

Communications Test Equipment

CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

ADF4252

ⴛ2

DOUBLER

OUTPUT

MUX

4-BIT R

COUNTER

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CHARGE

PUMP

REFERENCE

REF

OUT

SET

24-BIT

DATA

CLK

DATA

ⴛ2

DOUBLER

15-BIT R

COUNTER

CHARGE

PUMP

PHASE

FREQUENCY

DETECTOR

MUXOUT

GND

1 A

GND

2 D

GND

1 CP

GND

FRACTIONAL N

RF DIVIDER

INTEGER N

IF DIVIDER

GENERAL DESCRIPTION

The ADF4252 is a dual fractional-N/integer-N frequency

synthesizer that can be used to implement local oscillators

(LO) in the upconversion and downconversion sections of

wireless receivers and transmitters. Both the RF and IF syn-

thesizers consist of a low noise digital PFD (phase frequency

detector), a precision charge pump, and a programmable refer-

ence divider. The RF synthesizer has a ⌺-⌬-based fractional

interpolator that allows programmable fractional-N division.

The IF synthesizer has programmable integer-N counters. A

complete PLL (phase-locked loop) can be implemented if the

synthesizer is used with an external loop filter and VCO (volt-

age controlled oscillator).

Control of all the on-chip registers is via a simple 3-wire inter-

face. The devices operate with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

Summary of content (28 pages)

PAGE 1
a Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 FEATURES 3.0 GHz Fractional-N/1.2 GHz Integer-N 2.7 V to 3.
PAGE 2
= V 3 = DV = 3 V ⴞ 10%, DV dBm referred to 50 ⍀, T = T ADF4252–SPECIFICATIONS1 (VR 1==2.7V k⍀, DD DD DD DD SET Parameter B Version Unit RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency 0.25/3.0 –10/0 0.1/3.
PAGE 3
ADF4252 (VDD1 = VDD2 = VDD3 = DVDD = 3 V ⴞ 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, TIMING CHARACTERISTICS* unless otherwise noted.) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 t7 10 10 10 25 25 10 20 ns min ns min ns min ns min ns min ns min ns min LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width *Guaranteed by design, but not production tested.
PAGE 4
ADF4252 ABSOLUTE MAXIMUM RATINGS 1, 2 ORDERING GUIDE (TA = 25°C, unless otherwise noted.) VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.
PAGE 5
ADF4252 PIN FUNCTION DESCRIPTIONS Mnemonic Function CPRF RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO. CPGND1 RF Charge Pump Ground. RFINA Input to the RF Prescaler. This small signal input is normally taken from the VCO. RFINB Complementary Input to the RF Prescaler. AGND1 Analog Ground for the RF Synthesizer.
PAGE 6
ADF4252 VDD1 VDD2 VDD3 DVDD VP1 RSET VP2 ADF4252 REFERENCE 4-BIT R COUNTER 2 DOUBLER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CPRF REFOUT VDD HIGH Z MUXOUT LOCK DETECT OUTPUT MUX DGND VDD RFINA N COUNTER RDIV RFINB NDIV CLK DATA LE THIRD ORDER FRACTIONAL INTERPOLATOR 24-BIT DATA REGISTER FRACTION REG MODULUS REG INTEGER REG 6-BIT IF A COUNTER IFINB IF PRESCALER IFINA 12-BIT IF B COUNTER 2 DOUBLER 15-BIT R COUNTER PHASE FREQUENCY DETECTOR AGND1 AGND2 DGND CHARGE PUMP
PAGE 7
Typical Performance Characteristics–ADF4252 TPC plots 1 to 12 attained using EVAL-ADF4252EB1; measurements from HP8562E spectrum analyzer. –10 –20 OUTPUT POWER (dB) –30 0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER (dB) 0 –40 –50 –60 –70 – 99.19dBc/Hz –80 –1kHz 1.7518GHz FREQUENCY 1kHz 0 VDD = 3V, VP = 5V ICP = 1.
PAGE 8
ADF4252 –20 OUTPUT POWER (dB) –30 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz 0 –10 REFERENCE LEVEL = – 4.2dBm –20 OUTPUT POWER (dB) 0 –10 –40 –50 –60 –70 –102dBc/Hz –80 –30 –40 –50 –70 –100 –2kHz –1kHz 1.7518GHz FREQUENCY 1kHz –400kHz 2kHz TPC 7. Phase Noise Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution OUTPUT POWER (dB) –30 VDD = 3V, VP = 5V ICP = 1.
PAGE 9
–70 –20 –75 –30 –80 –40 SPURIOUS LEVEL (dBc) PHASE NOISE (dBc/Hz) ADF4252 –85 LOWEST SPUR MODE –90 –95 –100 LOW NOISE AND SPUR MODE –105 LOWEST NOISE MODE –110 –50 –60 –70 –80 –90 –100 –115 –110 –120 1.430 1.435 1.440 1.445 1.450 1.455 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.460 FREQUENCY (GHz) –10 –20 –20 –30 –30 –40 –40 LOWEST NOISE MODE –50 –60 –70 –80 –60 –70 –90 –100 –110 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.
PAGE 10
0 –120 –5 –130 VDD = 3V VP = 3V PHASE NOISE (dB/Hz) AMPLITUDE (dBm) ADF4252 –10 PRESCALER = 4/5 –15 –20 PRESCALER = 8/9 –25 0 1 2 3 4 FREQUENCY (GHz) 5 –160 –180 10k 6 TPC 19. RF Input Sensitivity 0 5 100k 1M PHASE DETECTOR FREQUENCY (Hz) 10M TPC 22. Phase Noise (Referred to CP Output) vs. PFD Frequency, IF Side 6 VDD = 3V VP2 = 3V 4 10 2 15 ICP (mA) IF INPUT POWER (dBm) –150 –170 –30 –35 –140 20 25 VDD = 3V VP1 = 5.5V 0 –2 30 –4 35 –6 40 –0.4 0.1 0.6 1.
PAGE 11
ADF4252 REFIN = the reference input frequency, D = RF REFIN doubler bit, R = the preset divide ratio of the binary 4-bit programmable reference counter (1 to 15), INT = the preset divide ratio of the binary 8-bit counter (31 to 255), MOD = the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095), and FRAC = the preset fractional ratio of the binary 12-bit programmable FRAC counter (0 to MOD). CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 3.
PAGE 12
ADF4252 Phase Frequency Detector (PFD) and Charge Pump Lock Detect The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 6 is a simplified schematic. The MUXOUT can be programmed for two types of lock detect: digital and analog. Digital is active high. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal.
PAGE 13
ADF4252 Table II.
PAGE 14
ADF4252 RESERVED Table III. RF N Divider Register Map 8-BIT RF INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P1 N8 N7 N6 P1 RESERVED 0 RESERVED N5 N4 N2 N3 CONTROL BITS 12-BIT RF FRACTIONAL VALUE (FRAC) N1 F12 F11 F10 F9 F8 F7 DB8 DB7 DB6 DB5 DB4 DB3 F6 F5 F4 F3 F2 F1 DB2 DB1 DB0 C3 (0) C2 (0) C1 (0) F12 0 0 0 0 . . . 1 F11 0 0 0 0 . . . 1 F10 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... ....
PAGE 15
ADF4252 PRESCALER RF REFIN DOUBLER Table IV. RF R Divider Register Map DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P3 P2 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3 (0) C2 (0) C1 (1) P2 RF REFIN DOUBLER 0 1 DISABLED ENABLED CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) 4-BIT RF R COUNTER M12 0 0 0 . . . 1 M11 0 0 0 . . . 1 M10 0 0 0 . . . 1 .......... .......... .......... .......... ..
PAGE 16
ADF4252 DB14 DB13 N3 T3 T2 DB12 T1 DB11 DB10 N2 CP2 DB9 DB8 CP1 0 RF POWERDOWN DB6 DB5 DB4 DB3 DB2 DB1 DB0 P8 N1 P6 P5 P4 C3 (0) C2 (1) C1 (0) RF COUNTER RESET DB7 RF CP THREESTATE NOISE AND SPUR SETTING 1 DB15 RF CP CURRENT SETTING RF PD POLARITY RESERVED RESERVED NOISE AND SPUR SETTING 2 NOISE AND SPUR SETTING 3 Table V.
PAGE 17
ADF4252 DB10 M4 REV. B M4 M3 M2 M1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COUNTER RESET CP THREESTATE MUXOUT POWERDOWN XO DISABLE Table VI.
PAGE 18
ADF4252 IF CP GAIN Table VII. IF N Divider Register Map DB23 P15 IF PRESCALER* DB22 P14 DB21 P13 P14 0 0 1 1 P15 IF CP GAIN 0 1 DISABLED ENABLED 12-BIT IF B COUNTER* DB20 B12 P13 0 1 0 1 DB19 DB18 B11 B10 DB17 B9 DB16 B8 DB15 B7 DB14 B6 6-BIT IF A COUNTER* DB13 DB12 B5 B4 DB11 B3 DB10 B2 DB9 B1 PRESCALER VALUE 8/9 16/17 32/33 64/65 B12 B11 B10 0 0 . . . 1 0 0 . . . 1 0 0 . . .
PAGE 19
ADF4252 IF REFIN DOUBLER Table VIII. IF R Divider Register Map DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C3 (1) C2 (0) C1 (1) P16 0 1 REV. B CONTROL BITS 15-BIT IF R COUNTER R15 0 0 0 0 . . . 32764 R14 0 0 0 0 . . . 1 R13 0 0 0 0 . . . 1 R12 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... ..........
PAGE 20
ADF4252 IF LDP IF POWERDOWN IF CP THREESTATE IF COUNTER RESET RESERVED DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP1 P21 P20 P19 P18 P17 C3 (1) C2 (1) C1 (0) IF CP CURRENT SETTING DB15 DB14 DB13 DB12 DB11 DB10 PR3 PR2 T8 T7 PR1 CP3 DB9 CP2 IF PD POLARITY RF PHASE RESYNC RF PHASE RESYNC Table IX.
PAGE 21
ADF4252 RF N DIVIDER REGISTER (Address R0) RF CONTROL REGISTER (Address R2) With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N divider register will be programmed. Table III shows the input data format for programming this register. With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register will be programmed. Table V shows the input data format for programming this register. Upon initialization, DB15–DB11 should all be set to 0.
PAGE 22
ADF4252 RF Phase Detector Polarity Lock Detect DB7 in the ADF4252 sets the RF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. The digital lock detect output goes high if there are 40 successive PFD cycles with an input error of less than 15 ns. It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles.
PAGE 23
ADF4252 delaying the resync activation until the locking transient is close to its final frequency. In the IF R divider register, Bits R5[17–3] are used to set a time interval from when the new channel is programmed to the time the resync is activated.
PAGE 24
ADF4252 So, from Equation 5: For example, in an application that requires 1.75 GHz RF and 200 kHz channel step resolution, the system has a 13 MHz reference signal. 1+ 0 = 13 MHz 1  FRAC  1.8 GHz = 13 MHz ×  INT + 65   FPFD = 13 MHz × One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. where INT = 138 and FRAC = 30.
PAGE 25
ADF4252 ± 100 kHz from the RF carrier. Harmonics of all spurs mentioned will also appear. With the lowest spur setting enabled, the spurs will be attenuated into the noise floor. byte has been written, the LE input should be brought high to complete the transfer. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). Prescaler The prescaler limits the INT value. With P = 4/5, Nmin = 31.
PAGE 26
ADF4252 R48 0 6.3V VDD VP VVCO 6.3V R44 0 VP R1 20 6.3V VVCO R49 0 6.3V 6.3V C7 22 F C11 22 F C29 22 F C8 10pF C12 10pF C30 10pF 6.3V VDD’ C10 10pF C6 10pF C15 100pF 14 VCC R12 18 R13 C16 18 100pF R14 18 10 RF OUT VIN 2 VCO2 VCO190–540T C19 2.2nF C18 270pF C23 10nF U1 C24 100nF ADF4252BCP R16 7.5k VCC 2 V IN C25 3.3nF R19 270 REFIN T13 J5 C14 1nF C43 100pF R47 0 3V 3 R46 0 O/P 4 B+ C45 10pF 2 GND Y3 R27 10k T16 R28 10k MUXOUT R27 2.
PAGE 27
ADF4252 OUTLINE DIMENSIONS 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters 0.60 MAX 4.0 BSC SQ PIN 1 INDICATOR 0.50 BSC 3.75 BSC SQ TOP VIEW 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX PIN 1 INDICATOR 0.60 MAX 24 1 19 18 13 12 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 REV. B 7 6 0.25 MIN 2.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 2.25 2.10 SQ 1.
PAGE 28
ADF4252 Revision History Location Page 10/03—Data Sheet changed from REV. A to REV. B. Change to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .