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Integrated Synthesizer and VCO

Data Sheet

ADF4360-2

Rev. C Document Feedback

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FEATURES

Output frequency range: 1850 MHz to 2170 MHz

Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable dual-modulus prescaler 8/9, 16/17, 32/33

Programmable output power level

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)

Test equipment

Wireless LANs

CATV equipment

GENERAL DESCRIPTION

The ADF4360-2 is a fully integrated integer-N synthesizer

and voltage-controlled oscillator (VCO). The ADF4360-2 is

designed for a center frequency of 2000 MHz. In addition, a

divide-by-2 option is available, whereby the user gets an RF

output of between 925 MHz and 1085 MHz.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

MUXOUT

VCO

REF

CLK

DATA

AGND DGND CPGND

SET

TUNE

OUT

VCO

CORE

PHASE

COMPARATOR

MUTE

DIVSEL = 2

DIVSEL = 1

N = (BP + A)

LOAD

CHARGE

PUMP

OUTPUT

STAGE

MULTIPLEXER

INTEGER

13-BIT B

COUNTER

14-BIT R

COUNTER

24-BIT

FUNCTION

LATCH

24-BIT

DATA REGISTER

5-BIT A

COUNTER

PRESCALER

P/P+1

MULTIPLEXER

LOCK

DETECT

÷2

ADF4360-2

04436-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Integrated Synthesizer and VCO ADF4360-2 Data Sheet FEATURES GENERAL DESCRIPTION Output frequency range: 1850 MHz to 2170 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4360-2 is a fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO).
PAGE 2
ADF4360-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect...................................................... 10 Applications ....................................................................................... 1 Input Shift Register .................................................................... 10 General Description .................................................................
PAGE 3
Data Sheet ADF4360-2 SPECIFICATIONS 1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency B Version Unit Conditions/Comments 10/250 MHz min/max REFIN Input Sensitivity 0.7/AVDD 0 to AVDD 5.0 ±100 V p-p min/max V max pF max µA max For f < 10 MHz, use a CMOS-compatible square wave, slew rate > 21 V/µs AC-coupled CMOS-compatible 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.
PAGE 4
ADF4360-2 Data Sheet Parameter RF OUTPUT CHARACTERISTICS5 VCO Output Frequency B Version Unit Conditions/Comments 1850/2170 MHz min/max ICORE = 20 mA, RF < 2 GHz ICORE = 15 mA, RF > 2 GHz VCO Sensitivity Lock Time 6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power Variation VCO Tuning Range NOISE CHARACTERISTICS5 VCO Phase-Noise Performance 8 57 400 6 15 −19 −37 −13/−6 ±3 1.25/2.
PAGE 5
Data Sheet ADF4360-2 TIMING CHARACTERISTICS 1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
ADF4360-2 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Maximum Junction Temperature CSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering Reflow 1 GND = AGND = DGND = 0 V. Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.
PAGE 7
Data Sheet ADF4360-2 19 LE 21 DVDD 20 MUXOUT 22 AGND 24 CP 23 CE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IDENTIFIER CPGND 1 AVDD 2 18 DATA 17 CLK AGND 3 ADF4360-2 RFOUTA 4 TOP VIEW (Not to Scale) 16 REFIN 15 DGND RFOUTB 5 14 CN VVCO 6 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 04436-003 CC 12 AGND 11 AGND 10 AGND 9 VTUNE 7 AGND 8 13 RSET Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4360-2 Data Sheet 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 1k –10 OUTPUT POWER (dB) –20 1 2 3 –40 –50 –70 10k 100k 1M FREQUENCY OFFSET (Hz) –2kHz 10M 0 –10 –20 –95 –100 –30 OUTPUT POWER (dB) –85 –90 –105 –110 –115 –120 –125 –130 –135 –40 2000MHz 1kHz 2kHz VDD = 3V, VVCO = 3V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES. BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz SWEEP = 140ms AVERAGES = 100 –50 –60 –79.
PAGE 9
Data Sheet ADF4360-2 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. N = BP + A 13-BIT B COUNTER LOAD PRESCALER P/P+1 FROM VCO 04436-011 N DIVIDER 100kΩ SW2 REFIN NC LOAD 5-BIT A COUNTER MODULUS CONTROL POWER-DOWN CONTROL NC TO PFD Figure 11.
PAGE 10
ADF4360-2 Data Sheet Table 5. C2 and C1 Truth Table MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 13 shows the MUXOUT section in block diagram form.
PAGE 11
Data Sheet ADF4360-2 OUTPUT STAGE The RFOUTA and RFOUTB pins of the ADF4360 family are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 15. To allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via Bit PL1 and Bit PL2 in the control latch. Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
PAGE 12
ADF4360-2 Data Sheet LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determines which latch is programmed. Table 6.
PAGE 13
Data Sheet ADF4360-2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG COUNTER RESET OUTPUT POWER LEVEL CP THREESTATE PHASE DETECTOR POLARITY CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLLD POWERDOWN 1 PRESCALER VALUE POWERDOWN 2 Table 7.
PAGE 14
ADF4360-2 Data Sheet RESERVED CP GAIN DIVIDEBY-2 DIVIDE-BY2 SELECT Table 8. N Counter Latch 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIVSEL DIV2 B2 B1 RSV A5 A4 A3 A2 A1 CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB1 DB0 C2 (1) C1 (0) THIS BIT IS NOT USED BY THE DEVICE AND IS A DON'T CARE BIT. B12 0 0 0 0 . . . 1 1 1 1 B11 0 0 0 0 . . . 1 1 1 1 .......... ....
PAGE 15
Data Sheet ADF4360-2 TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED Table 9. R Counter Latch BAND SELECT CLOCK ANTIBACKLASH PULSE WIDTH CONTROL BITS 14-BIT REFERENCE COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 RSV R8 R7 R6 R5 R4 R3 R2 R1 RSV BSC2 BSC1 TMB TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL OPERATION. LDP 0 1 BSC1 0 1 0 1 R13 R12 R11 R10 R14 0 0 0 0 . . .
PAGE 16
ADF4360-2 Data Sheet POWER-UP Power-Up Sequence The correct programming sequence for the ADF4360-2 after power-up is as: 1. R counter latch 2. Control latch 3. N counter latch Initial Power-Up Initial power-up refers to programming the part after the application of voltage to the AVDD, DVDD, VVCO, and CE pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch.
PAGE 17
Data Sheet ADF4360-2 Hardware Power-Up/Power-Down Software Power-Up/Power-Down If the ADF4360-2 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the correct frequency because it is already in the correct frequency band. The lock time depends on the value of capacitance on the CN pin, which is <5 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.
PAGE 18
ADF4360-2 Data Sheet CONTROL LATCH Charge Pump Currents With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. CPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1. Prescaler Value CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7. In the ADF4360 family, P2 and P1 in the control latch set the prescaler values.
PAGE 19
Data Sheet ADF4360-2 N COUNTER LATCH R COUNTER LATCH With (C2, C1) = (1, 0), the N counter latch is programmed. Table 8 shows the input data format for programming the N counter latch. With (C2, C1) = (0, 1), the R counter latch is programmed. Table 9 shows the input data format for programming the R counter latch. A Counter Latch R Counter A5 to A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). R1 to R14 set the counter divide ratio. The divide range is 1 (00......
PAGE 20
ADF4360-2 Data Sheet APPLICATIONS DIRECT CONVERSION MODULATOR The LO ports of the AD8349 can be driven differentially from the complementary RFOUTA and RFOUTB outputs of the ADF4360-2. This gives better performance than a single-ended LO driver and eliminates the often necessary use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the AD8349. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 2.1°.
PAGE 21
Data Sheet ADF4360-2 FIXED FREQUENCY LO ADuC812 Interface Figure 18 shows the ADF4360-2 used as a fixed frequency LO at 2.0 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360-2 is 8 MHz. Because using a larger PFD frequency allows the use of a smaller N, the in-band phase noise is reduced to as low as possible, –99 dBc/Hz.
PAGE 22
ADF4360-2 Data Sheet VVCO The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package.
PAGE 23
Data Sheet ADF4360-2 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 3.75 BSC SQ 1 0.50 BSC 2.45 2.30 SQ 2.15 EXPOSED PAD 6 13 TOP VIEW 1.00 0.85 0.80 12° MAX 7 12 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 24
ADF4360-2 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04436–0–11/12(C) Rev.