Integrated Synthesizer and VCO ADF4360-7 Data Sheet FEATURES GENERAL DESCRIPTION Output frequency range: 350 MHz to 1800 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4360-7 is an integrated integer-N synthesizer and voltage controlled oscillator (VCO).
ADF4360-7 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect...................................................... 11 Applications ....................................................................................... 1 Input Shift Register .................................................................... 11 General Description .................................................................
Data Sheet ADF4360-7 SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 2 CHARGE PUMP ICP Sink/Source 3 High Value Low Value RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs.
ADF4360-7 Parameter RF OUTPUT CHARACTERISTICS5 Maximum VCO Output Frequency Data Sheet B Version Unit Conditions/Comments 1800 MHz ICORE = 5 mA. Depending on L. See the Choosing the Correct Inductance Value section. Minimum VCO Output Frequency VCO Output Frequency 350 490/585 MHz MHz min/max VCO Frequency Range VCO Sensitivity 1.2 12 Ratio MHz/V typ 400 6 15 −19 −9 −14/−5 ±3 1.25/2.5 µs typ MHz/V typ kHz typ dBc typ dBc typ dBm typ dB typ V min/max −116 −138 −144 −148 −172 −163 −147 −92 0.
Data Sheet ADF4360-7 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2.
ADF4360-7 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Peak Soldering Reflow Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.
Data Sheet ADF4360-7 19 LE PIN 1 IDENTIFIER CPGND 1 AVDD 2 AGND 3 ADF4360-7 RFOUTA 4 TOP VIEW (Not to Scale) 18 DATA 17 CLK 16 REFIN RSET CC 12 13 AGND 11 VVCO 6 L2 10 CN L1 9 14 VTUNE 7 DGND RFOUTB 5 AGND 8 15 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 04441-003 20 MUXOUT 21 DVDD 22 AGND 23 CE 24 CP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
ADF4360-7 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –40 0 –50 –10 –20 –70 OUTPUT POWER (dB) –80 –90 –100 –110 –120 –130 –30 –40 –50 –60 –96.4dBc/Hz –70 04441-004 –80 –140 –150 100 1k 10k 100k FREQUENCY OFFSET (Hz) 1M –90 10M –2kHz –70 –20 OUTPUT POWER (dB) 1kHz 2kHz –105 –110 –115 –120 –125 –130 –30 VDD = 3.3V, VVCO = 3.3V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES.
ADF4360-7 –40 0 –50 –10 –60 –20 –70 OUTPUT POWER (dB) –80 –90 –100 –110 –120 –50 –60 1k 10k 100k FREQUENCY OFFSET (Hz) 1M –2kHz 10M 1.25GHz 1kHz 2kHz 0 –75 REFERENCE LEVEL = –3dBm –10 –80 –85 –90 –95 –100 OUTPUT POWER (dB) –20 –105 –110 –115 –120 –125 –130 –30 VDD = 3.3V, VVCO = 3.3V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES.
ADF4360-7 Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. N = BP + A 13-BIT B COUNTER LOAD PRESCALER P/P+1 FROM VCO POWER-DOWN CONTROL 5-BIT A COUNTER MODULUS CONTROL 100k N DIVIDER SW2 REFIN NC LOAD 04441-017 NC TO PFD Figure 17.
Data Sheet ADF4360-7 Table 5. C2 and C1 Truth Table MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 19 shows the MUXOUT section in block diagram form. Control Bits C1 0 1 0 1 C2 0 0 1 1 Lock Detect MUXOUT can be programmed for two types of lock detect: digital and analog.
ADF4360-7 Data Sheet After band selection, normal PLL action resumes. The value of KV is determined by the value of inductors used (see the Choosing the Correct Inductance section). If divide-by2 operation has been selected (by programming DIV2 [DB22] high in the N counter latch), the value is halved. The ADF4360 family contains linearization circuitry to minimize any variation of the product of ICP and KV.
Data Sheet ADF4360-7 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed. Table 6.
ADF4360-7 Data Sheet DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG COUNTER RESET OUTPUT POWER LEVEL CP THREESTATE PHASE DETECTOR POLARITY CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLLD POWERDOWN 1 PRESCALER VALUE POWERDOWN 2 Table 7.
Data Sheet ADF4360-7 RESERVED CP GAIN DIVIDEBY-2 DIVIDE-BY2 SELECT Table 8. N Counter Latch 13-BIT B COUNTER CONTROL BITS 5-BIT A COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIVSEL DIV2 B2 B1 RSV A5 A4 A3 A2 A1 CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB1 DB0 C2 (1) C1 (0) THIS BIT IS NOT USED BY THE DEVICE AND IS A DON'T CARE BIT. A5 0 0 0 0 . . . 1 1 1 1 B12 0 0 0 0 . . . 1 1 1 1 B11 0 0 0 0 . .
ADF4360-7 Data Sheet TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED Table 9. R Counter Latch BAND SELECT CLOCK ANTIBACKLASH PULSE WIDTH CONTROL BITS 14-BIT REFERENCE COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 RSV R8 R7 R6 R5 R4 R3 R2 R1 RSV BSC2 BSC1 TMB TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL OPERATION. LDP 0 1 BSC1 0 1 0 1 R13 R12 R11 R10 R9 R14 0 0 0 0 . . .
Data Sheet ADF4360-7 POWER-UP Power-Up Sequence The correct programming sequence for the ADF4360-7 after power-up is: 1. R counter latch 2. Control latch 3. N counter latch Initial Power-Up Initial power-up refers to programming the part after the application of voltage to the AVDD, DVDD, VVCO and CE pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch.
ADF4360-7 Data Sheet Hardware Power-Up/Power-Down Software Power-Up/Power-Down If the part is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the correct frequency, because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the CN pin, which is <10 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.
Data Sheet ADF4360-7 CONTROL LATCH Charge Pump Currents With (C2, C1) = (0,0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. CPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1. Prescaler Value CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7. In the ADF4360 family, P2 and P1 in the control latch set the prescaler values.
ADF4360-7 Data Sheet N COUNTER LATCH R COUNTER LATCH Table 8 shows the input data format for programming the N counter latch. With (C2, C1) = (0, 1), the R counter latch is programmed. Table 9 shows the input data format for programming the R counter latch. A Counter Latch R Counter A5 to A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). R1 to R14 set the counter divide ratio. The divide range is 1 (00......001) to 16383 (111......111).
Data Sheet ADF4360-7 APPLICATIONS FREQUENCY GENERATOR This allows frequencies as low as 8 MHz and as high as 137 MHz to be generated using a single system. In the circuit drawn in Figure 23, the ADF4360-7 is being used to generate 1024 MHz, and the ADF4007 is being used to divide by 8. To provide a channel spacing of 100 kHz, a PFD frequency of 800 kHz is used for the ADF4360-7 PLL. The loop bandwidth is chosen to be 20 kHz.
ADF4360-7 Data Sheet 35 CHOOSING THE CORRECT INDUCTANCE VALUE FO = 1 2π 6.2 pF(0.9 nH + L EXT ) where FO is the center frequency, and LEXT is the external inductance. 1500 1400 1300 FREQUENCY (MHz) 1200 1100 1000 900 25 20 15 10 5 0 04441-029 As shown in Figure 24, the lowest commercially available value of inductance, 1.0 nH, sets the center frequency at approximately 1300 MHz. For inductances less than 2.4 nH, a PCB trace should be used, a direct short.
Data Sheet ADF4360-7 INTERFACING ADSP-2181 Interface The ADF4360 family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table.
ADF4360-7 Data Sheet VVCO OUTPUT MATCHING VVCO 51Ω 47nH 3.9pF 7.5nH RFOUT 50Ω 04441-034 There are a number of ways to match the output of the ADF4360-7 for optimum operation; the most basic is to use a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series, as shown in Figure 29. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in this circuit typically gives −5 dBm output power into a 50 Ω load. Figure 30.
Data Sheet ADF4360-7 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 3.75 BSC SQ 1 0.50 BSC 2.45 2.30 SQ 2.15 EXPOSED PAD 6 13 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 7 12 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
ADF4360-7 Data Sheet NOTES Rev.
Data Sheet ADF4360-7 NOTES Rev.
ADF4360-7 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04441-0-3/13(D) Rev.