Datasheet

ADG441/ADG442/ADG444 Data Sheet
Rev. B | Page 12 of 16
TRENCH ISOLATION
In the ADG441A, ADG442A, and ADG444A, an insulating
oxide layer (trench) is placed between the NMOS and the
PMOS transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated
switches, are eliminated, and the result is a completely latch-up
proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
Figure 21. Trench Isolation
05233-004
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
TRENCH
P-WELL N-WELL
LOCO
NMOS PMOS