Datasheet

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Super Sequencer with Margining Control

ADM1069

Rev. C

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FEATURES

Complete supervisory and sequencing solution for up to

8 supplies

8 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures

4 selectable input attenuators allow supervision of supplies to

14.4 V on VH

6 V on VP1 to VP3 (VPx)

4 dual-function inputs, VX1 to VX4 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

8 programmable driver outputs, PDO1 to PDO8 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open-collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events

Enables complex control of boards

Power-up and power-down sequence control

Fault event handling

Interrupt generation on warnings

Watchdog function can be integrated in SE

Program software control of sequencing through SMBus

Complete voltage margining solution for 4 voltage rails

4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node

12-bit ADC for readback of all supervised voltages

Reference input (REFIN) has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy

User EEPROM: 256 bytes

Industry-standard 2-wire bus interface (SMBus)

Guaranteed PDO low with VH, VPx = 1.2 V

Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,

6 mm × 6 mm LFCSP packages

For more information about the ADM1069 register map,

refer to the AN-721 Application Note at

www.analog.com

FUNCTIONAL BLOCK DIAGRAM

04735-001

PDO7

PDO8

PDOGND

VDDCA P

VDD

ARBITRATOR

DAC1

OUT

DAC

DAC2

OUT

DAC

DAC3

OUT

DAC

DAC4

OUT

DAC

GND

VCCP

VX1

VX2

VP1

VP2

VP3

GND

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

CONFIGURABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

VX3

VX4

SDA SCL A1 A0

SMBus

INTERFACE

REFIN REFOUT REFGND

VREF

12-BIT

SAR ADC

MUX

EEPROM

CLOSED-LOOP

MARGINING SYSTEM

ADM1069

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

SFDs)

SEQUENCING

ENGINE

CONFIGURABLE

OUTPUT

DRIVERS

(HV CAPABLE OF

DRIVING GATES

OF N-FET)

Figure 1.

APPLICATIONS

Central office systems

Servers/routers

Multivoltage system line cards

DSP/FPGA supply sequencing

In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1069 Super Sequencer® is a configurable supervisory/

sequencing device that offers a single-chip solution for supply

monitoring and sequencing in multiple supply systems. In addition

to these functions, the ADM1069 integrates a 12-bit ADC and

four 8-bit voltage output DACs. These circuits can be used to

implement a closed-loop margining system that enables supply

adjustment by altering either the feedback node or reference of

a dc-to-dc converter using the DAC outputs.

Summary of content (32 pages)

PAGE 1
Super Sequencer with Margining Control ADM1069 FEATURES FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT REFGND ADM1069 SDA SCL A1 A0 SMBus INTERFACE VREF 12-BIT SAR ADC MUX EEPROM CLOSED-LOOP MARGINING SYSTEM VX1 VX2 VX3 VX4 DUALFUNCTION INPUTS CONFIGURABLE OUTPUT DRIVERS PDO1 (LOGIC INPUTS OR SFDs) (HV CAPABLE OF DRIVING GATES OF N-FET) PDO4 PDO2 PDO3 PDO5 PDO6 SEQUENCING ENGINE VP1 VP3 PROGRAMMABLE RESET GENERATORS VH (SFDs) VP2 CONFIGURABLE OUTPUT DRIVERS (LV CAPABLE OF DRIVING LOGIC SIGN
PAGE 2
ADM1069 TABLE OF CONTENTS Features .............................................................................................. 1 SMBus Jump (Unconditional Jump)........................................ 17 Functional Block Diagram .............................................................. 1 Sequencing Engine Application Example ............................... 18 Applications....................................................................................... 1 Fault and Status Reporting.........
PAGE 3
ADM1069 The logical core of the device is a sequencing engine (SE). This state machine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs. Supply margining can be performed with a minimum of external components.
PAGE 4
ADM1069 SPECIFICATIONS VH = 3.0 V to 14.4 V,1 VPx = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPx VPx VH VDDCAP CVDDCAP Min Typ Max Unit Test Conditions/Comments 4.75 6.0 14.4 5.4 V V V V μF Minimum supply required on one of VH, VPx Maximum VDDCAP = 5.1 V, typical VDDCAP = 4.75 V Regulated LDO output Minimum recommended decoupling capacitance 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO8 off, DACs off, ADC off mA 3.0 2.
PAGE 5
ADM1069 Parameter ANALOG-TO-DIGITAL CONVERTER Signal Range Min 0 Input Reference Voltage on REFIN Pin, VREFIN Resolution INL Gain Error Conversion Time REFERENCE OUTPUT Reference Output Voltage Load Regulation Minimum Load Capacitance PSRR PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode (PDO1 to PDO6) Output Impedance VOH IOUTAVG Max Unit Test Conditions/Comments VREFIN V The ADC can convert signals presented to the VH, VPx, and VXx pins; VPx and VH input signals are attenuated dependin
PAGE 6
ADM1069 Parameter Standard (Digital Output) Mode (PDO1 to PDO8) VOH Min Typ Max Unit Test Conditions/Comments 0.50 20 60 29 2 V V V V mA mA kΩ mA 10 110 μA kHz VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA VPU to VPx = 6.0 V, IOH = 0 mA VPU ≤ 2.7 V, IOH = 0.
PAGE 7
ADM1069 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2.
PAGE 8
ADM1069 40 39 38 37 36 35 34 33 32 31 25 24 PIN 1 INDICATOR ADM1069 TOP VIEW (Not to Scale) 17 8 NC 1 VX1 2 VX2 3 VX3 4 VX4 5 NC 6 VP1 7 VP2 8 VP3 9 VH 10 PIN 1 INDICATOR ADM1069 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 PDO7 PDO8 NC NC 04735-003 11 12 13 14 15 16 17 18 19 20 16 NOTES 1. NC = NO CONNECT. 2. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM. THIS PAD IS A NO CONNECT (NC).
PAGE 9
ADM1069 LQFP 31 32 1 2 Pin No. LFCSP 1 39 40 Mnemonic VDDCAP GND2 Description Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V. Note that a capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for this purpose. Supply Ground. The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.
PAGE 10
ADM1069 TYPICAL PERFORMANCE CHARACTERISTICS 180 6 160 5 140 120 IVP1 (µA) VVDDCAP (V) 4 3 100 80 60 2 40 1 0 1 2 3 4 5 0 6 04735-053 04735-050 0 20 0 1 2 3 VVP1 (V) 4 5 6 VVP1 (V) Figure 5. VVDDCAP vs. VVP1 Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply) 6 5.0 4.5 5 4.0 3.5 3.0 IVH (mA) 3 2 2.0 1.5 1.0 04735-051 1 0 2.5 0 2 4 6 8 10 12 14 04735-054 VVDDCAP (V) 4 0.5 0 16 0 2 4 6 VVH (V) 8 10 12 14 16 VVH (V) Figure 6. VVDDCAP vs.
PAGE 11
ADM1069 14 1.0 0.8 0.6 10 0.4 8 0.2 DNL (LSB) 6 0 –0.2 –0.4 4 –0.6 0 04735-056 2 0 2.5 5.0 7.5 10.0 12.5 04735-066 CHARGE-PUMPED V PDO1 (V) 12 –0.8 –1.0 15.0 0 1000 5.0 1.0 4.5 0.8 4.0 0.6 3.5 0.4 VP1 = 5V 2.5 VP1 = 3V 0.2 0 –0.2 1.5 –0.4 1.0 –0.6 0.5 0 1 2 3 4000 4 5 04735-063 INL (LSB) 3.0 0 3000 Figure 14. DNL for ADC 04735-057 VPDO1 (V) Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD 2.0 2000 CODE ILOAD (µA) –0.8 –1.
PAGE 12
ADM1069 1.005 1.004 1.003 DAC 20kΩ BUFFER OUTPUT 47pF PROBE POINT DAC OUTPUT 1.002 1.001 VP1 = 3.0V 1.000 VP1 = 4.75V 0.999 0.998 04735-059 CH1 200mV M1.00µs CH1 04735-065 0.997 1 0.996 756mV 0.995 –40 –20 0 20 40 60 80 100 80 100 TEMPERATURE (°C) Figure 19. DAC Output vs. Temperature Figure 17. Transient Response of DAC Code Change into Typical Load 2.058 DAC 100kΩ BUFFER OUTPUT 1V PROBE POINT REFOUT (V) 2.053 VP1 = 3.0V 2.048 VP1 = 4.75V 04735-060 1 CH1 200mV M1.
PAGE 13
ADM1069 POWERING THE ADM1069 An external capacitor to GND is required to decouple the onchip supply from noise. This capacitor should be connected to the VDDCAP pin, as shown in Figure 21. The capacitor has another use during brownouts (momentary loss of power). Under these conditions, when the input supply (VPx or VH) dips transiently below VDD, the synchronous rectifier switch immediately turns off so that it does not pull VDD down.
PAGE 14
ADM1069 INPUTS SUPPLY SUPERVISION The threshold value required is given by The ADM1069 has eight programmable inputs. Four of these are dedicated supply fault detectors (SFDs). These dedicated inputs are called VH and VPx (VP1 to VP3) by default. The other four inputs are labeled VXx (VX1 to VX4) and have dual functionality. They can be used either as SFDs, with functionality similar to the VH and VPx, or as CMOS-/TTL-compatible logic inputs to the device.
PAGE 15
ADM1069 The hysteresis value is given by VHYST = VR × NTHRESH/255 where: VHYST is the desired hysteresis voltage. NTHRESH is the decimal value of the 5-bit hysteresis code. Note that NTHRESH has a maximum value of 31. The maximum hysteresis for the ranges is listed in Table 6. INPUT GLITCH FILTERING The final stage of the SFDs is a glitch filter.
PAGE 16
ADM1069 OUTPUTS The data driving each of the PDOs can come from one of three sources. The source can be enabled in the PDOxCFG configuration register (see the AN-721 Application Note for details). The data sources are as follows: SUPPLY SEQUENCING THROUGH CONFIGURABLE OUTPUT DRIVERS Supply sequencing is achieved with the ADM1069 using the programmable driver outputs (PDOs) on the device as control signals for supplies. The output drivers can be used as logic enables or as FET drivers.
PAGE 17
ADM1069 SEQUENCING ENGINE OVERVIEW The SE state machine comprises 63 state cells. Each state has the following attributes: • • • • • • Monitors signals indicating the status of the eight input pins, VP1 to VP3, VH, and VX1 to VX4. Can be entered from any other state. Three exit routes move the state machine onto a next state: sequence detection, fault monitoring, and timeout. Delay timers for the sequence and timeout blocks can be programmed independently, and changed with each state change.
PAGE 18
ADM1069 SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE. Figure 28 shows how the simple building block of a single SE state can be used to build a power-up sequence for a three-supply system. Table 8 lists the PDO outputs for each state in the same SE implementation. In this system, a good 5 V supply on VP1 and the VX1 pin held low are the triggers required to start a power-up sequence. The sequence next turns on the 3.3 V supply, then the 2.
PAGE 19
ADM1069 Monitoring Fault Detector Timeout Detector The monitoring fault detector block is used to detect a failure on an input. The logical function implementing this is a wide OR gate that can detect when an input deviates from its expected condition. The clearest demonstration of the use of this block is in the PWRGD state, where the monitor block indicates that a failure on one or more of the VP1, VP2, or VP3 inputs has occurred.
PAGE 20
ADM1069 VOLTAGE READBACK The ADM1069 has an on-board, 12-bit, accurate ADC for voltage readback over the SMBus. The ADC has an 8-channel analog mux on the front end. The eight channels consist of the eight SFD inputs (VH, VPx, and VXx). Any or all of these inputs can be selected to be read, in turn, by the ADC. The circuit controlling this operation is called the round-robin circuit. This circuit can be selected to run through its loop of conversions once or continuously.
PAGE 21
ADM1069 SUPPLY MARGINING OVERVIEW CLOSED-LOOP SUPPLY MARGINING It is often necessary for the system designer to adjust supplies, either to optimize their level or force them away from nominal values to characterize the system performance under these conditions. This is a function typically performed during an in-circuit test (ICT), such as when a manufacturer wants to guarantee that a product under test functions correctly at nominal supplies minus 10%.
PAGE 22
ADM1069 MICROCONTROLLER VIN ADM1069 VH/VPx/VXx DC-TO-DC CONVERTER MUX ATTENUATION RESISTOR DACx FEEDBACK GND ADC DAC DEVICE CONTROLLER (SMBus) PCB TRACE NOISE DECOUPLING CAPACITOR 04735-034 OUTPUT Figure 33. Closed-Loop Margining System Using the ADM1069 WRITING TO THE DACS Four DAC ranges are offered. They can be placed with midcode (Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are placed to correspond to the most common feedback voltages.
PAGE 23
ADM1069 APPLICATIONS DIAGRAM 12V IN 12V OUT 5V IN 5V OUT 3V IN 3V OUT IN DC-TO-DC1 EN 5V OUT 3V OUT 3.3V OUT VP1 VP2 VP3 1.25V OUT 1.2V OUT 0.9V OUT VX1 VX2 VX3 IN DC-TO-DC2 PDO3 PDO4 PDO5 PDO7 VX4 EN DAC1 SYSTEM RESET 10µF IN EN OUT 1.2V OUT 3.3V OUT IN EN *ONLY ONE MARGINING CIRCUIT SHOWN FOR CLARITY. DAC1 TO DAC4 ALLOW MARGINING FOR UP TO FOUR VOLTAGE RAILS. 1.25V OUT DC-TO-DC3 REFIN VCCP VDDCAP GND 10µF OUT PWRGD PDO8 REFOUT 10µF 3.
PAGE 24
ADM1069 COMMUNICATING WITH THE ADM1069 CONFIGURATION DOWNLOAD AT POWER-UP The configuration of the ADM1069 (undervoltage/overvoltage thresholds, glitch filter timeouts, PDO configurations, and so on) is dictated by the contents of the RAM. The RAM comprises digital latches that are local to each of the functions on the device. The latches are double-buffered and have two identical latches, Latch A and Latch B.
PAGE 25
ADM1069 SMBus E E P R O M L D DEVICE CONTROLLER R A M L D D A T A U P D LATCH A LATCH B EEPROM FUNCTION (OV THRESHOLD ON VP1) 04735-035 POWER-UP (VCC > 2.5V) Figure 35. Configuration Update Flow Diagram UPDATING THE SEQUENCING ENGINE Sequencing engine (SE) functions are not updated in the same way as regular configuration latches. The SE has its own dedicated 512-byte EEPROM for storing state definitions, providing 63 individual states, each with a 64-bit word (one state is reserved).
PAGE 26
ADM1069 The device also has several identification registers (read-only) that can be read across the SMBus. Table 12 lists these registers with their values and functions. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Table 12.
PAGE 27
ADM1069 1 9 1 9 SCL 0 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 ACK. BY SLAVE START BY MASTER 1 SCL (CONTINUED) SDA (CONTINUED) D7 FRAME 1 SLAVE ADDRESS D6 D5 D4 D3 9 D2 FRAME 3 DATA BYTE D1 D0 ACK. BY MASTER D0 1 D7 FRAME 2 DATA BYTE D6 D5 ACK. BY MASTER D4 9 D3 D2 FRAME N DATA BYTE D1 D0 NO ACK. STOP BY MASTER Figure 37.
PAGE 28
ADM1069 Data can be written to and read from both the RAM and the EEPROM as single data bytes. Data can be written only to unprogrammed EEPROM locations. To write new data to a programmed location, the location contents must first be erased. EEPROM erasure cannot be done at the byte level. The EEPROM is arranged as 32 pages of 32 bytes each, and an entire page must be erased. • 1 S • WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations.
PAGE 29
ADM1069 Write Byte/Word Block Write In a write byte/word operation, the master device sends a command byte and one or two data bytes to the slave device, as follows: In a block write operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously.
PAGE 30
ADM1069 9. The ADM1069 uses the following SMBus read protocols. Receive Byte In a receive byte operation, the master device receives a single byte from a slave device, as follows: 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts an ACK on SDA. The master receives a data byte. The master asserts a NACK on SDA. The master asserts a stop condition on SDA, and the transaction ends.
PAGE 31
ADM1069 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 9.00 BSC SQ 32 25 1 24 PIN 1 7.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE 8 17 9 16 0.45 0.37 0.30 0.80 BSC LEAD PITCH VIEW A VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBA Figure 48. 32-Lead Low Profile Quad Flat Package [LQFP] (ST-32-2) Dimensions shown in millimeters 6.00 BSC SQ 0.60 MAX 0.60 MAX TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.