Datasheet

Data Sheet ADM1186
Rev. B | Page 15 of 28
The action taken by the ADM1186 state machine is the same
for an internal or external fault. The state machine enters the
SET FAULT state, asserts the SEQ_DONE and
FAULT
pins low
(ADM1186-1 only), and asserts all four OUTx enable pins low.
The ADM1186 remains in the SET FAULT state for the fault
hold time before moving into the CLEAR FAULT state. If the
UP or UP/
DOWN
pin is low for a time of t ≥ t
UDOUT
before the
state machine enters the CLEAR FAULT state, the state machine
can move immediately into the WAIT ALL OK state.
The length of time from entering the SET FAULT state to
reaching the WAIT ALL OK state, with the UP or UP/
DOWN
pin held low, is the fault hold time. The fault hold time is the
minimum amount of time that the
FAULT
pin is held low. If the
UP or UP/
DOWN
pin is high when the state machine enters
the CLEAR FAULT state, the time that the
FAULT
pin is held
low is extended.
When the ADM1186-1 is in the CLEAR FAULT state and the
UP pin is low, the WAIT ALL OK state is entered and the
FAULT
pin is deasserted. If an external device is driving the
FAULT
pin low, the state machine remains in the WAIT ALL
OK state until the
FAULT
pin returns high. The state machine
then transitions into the WAIT START state, ready for the next
power-up sequence.
DEFINING TIME DELAYS
The ADM1186 allows the user to define sequence and blanking
time delays using capacitors. The ADM1186-1 has four
DLY_EN_OUTx pins, and the ADM1186-2 has three
DLY_EN_OUTx pins. Capacitors connected to these pins
control the time delay between supplies turning on or off
during the power-up and power-down sequences. Both devices
provide one pin (BLANK_DLY) to set the blanking time delay.
The ADM1186-1 has a pin called DLY_EN_OUT1 that the
ADM1186-2 does not have. The capacitor on this pin sets the
time delay used before enabling OUT1 during a power-up
sequence, as well as the time delay between disabling OUT1 and
returning to the WAIT START state during a power-down
sequence. Although this time delay is not essential when a
single ADM1186-1 device is used, the time delay is essential
when multiple devices are cascaded (see the Cascading Multiple
Devices section).
When ADM1186-1 devices are used in cascade, the capacitor
on the DLY_EN_OUT1 pin of Device N + 1 sets the sequence
time delay between the last supply of Device N and the first
supply of Device N + 1 being turned on and off.
During the power-up sequence, the capacitors connected to the
DLY_EN_OUTx pins set the time from the end of the blanking
period to the next enable output being asserted high. During
the power-down sequence, the capacitors set the time between
consecutive enable outputs being asserted low.
The blanking time is controlled by the capacitor on the
BLANK_DLY pin. This capacitor sets the time allowed between
an enable output being asserted, turning on a supply, and the
output of the supply rising above its defined UV threshold.
A constant current source is connected to a capacitor through a
switch that is under the control of the state machine. This current
source charges a capacitor until the threshold voltage is reached.
For all capacitors, the duration of the time delay is defined by
the following formula:
t
DELAY
= C
DELAY
× 0.1
where:
t
DE LAY
is the time delay in seconds.
C
DE LAY
is the capacitor value in microfarads (µF).
For capacitor values from 10 nF to 2.2 μF, the time delay is in
the range of 1 ms to 220 ms. If a capacitor is not connected to
a timing pin, the time delay is minimal, in the order of several
microseconds.
When a capacitor is not being charged by the current source,
it is connected via a resistor to ground. Each capacitor has a
dedicated resistor with a typical value of 450 Ω. To ensure
accurate time delays, time must be allowed for a capacitor to
discharge after it has been used. Typically, allowing five RC time
constants is sufficient for the capacitor to discharge to less than
1% of the threshold voltage.
If the capacitors are not sufficiently discharged after use, the
time delays will be smaller than expected. This can happen if
very small capacitor values are used or if a power-up or power-
down sequence is performed immediately after another
sequence has been completed. Examples of when this behavior
can occur include, but are not limited to, the following:
• A power-down sequence is initiated immediately after
entering the POWER-UP DONE state.
• A fault occurs in the ENABLE OUT1 state when the
DLY_EN_OUT1 capacitor is charged and a power-up
sequence is started very quickly after the fault has been
handled.
• The DLY_EN_OUTx time delay is very short and is insuffi-
cient to allow the BLANK_DLY capacitor to fully discharge.
To achieve the best timing accuracy over the operational
temperature range, the choice of capacitor is critical. Capacitors
are typically specified with a value tolerance of ±5%, ±10%, or
±20%, but in addition to the value tolerance, there is also a
variation in capacitance over temperature.
Where high accuracy timing is important, the use of capacitors
that use a C0G, sometimes called NPO, dielectric results in a
capacitance variation of only ±0.3% over the full temperature
range. This capacitance variation contrasts with typical varia-
tions of ±15% for X5R and X7R dielectrics and ±22% for X7S
capacitor dielectrics.