Datasheet

ADM4850–ADM4857
Rev. 0 | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1 V
CC
8
DI
4 GND 5
ADM4850/
ADM4851/
ADM4852/
ADM4853
TOP VIEW
(Not to Scale)
RE
2 B 7
04931-002
DE
A 63
Figure 2. ADM4850–ADM4853 Pin Configuration
Table 8. ADM4850–ADM4853 Pin Descriptions
Pin No. Mnemonic Description
1 RO
Receiver Output. When enabled, if (A−B) ≥ −30 mV, then RO = high.
If (A−B) ≤ −200 mV, then RO = low.
2
RE Receiver Output Enable.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
3 DE
Driver Output Enable. A high level enables the driver differential inputs A and B.
A low level places it in a high impedance state.
4 DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high,
while a logic high on DI forces A high and B low.
5 GND Ground.
6 A Noninverting Receiver Input A/Driver Output A.
7 B Inverting Receiver Input B/Driver Output B.
8 V
CC
5 V Power Supply.
V
CC
1
A 8
GND
4 Y 5
ADM4854/
ADM4855/
ADM4856/
ADM4857
TOP VIEW
(Not to Scale)
RO
2 B 7
04931-003
DI
Z 63
Figure 3. ADM4854–ADM4857 Pin Configuration
Table 9. ADM4854–ADM4857 Pin Descriptions
Pin No. Mnemonic Description
1 V
CC
5 V Power Supply.
2 RO
Receiver Output. When enabled, if (A−B) ≥ −30 mV, then RO = high.
If (A−B) ≤ −200 mV, then RO = low.
3 DI
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high,
while a logic high on DI forces Y high and Z low.
4 GND Ground.
5 Y Driver Noninverting Output.
6 Z Driver Inverting Output.
7 B Receiver Inverting Input.
8 A Receiver Noninverting Input.