Datasheet

ADM8690/ADM8691/ADM8695 Data Sheet
Rev. C | Page 12 of 24
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the selected
timeout period, a
RESET
pulse is generated.
The nominal watchdog timeout period is preset at 1.6 sec on
the ADM8690. The ADM8691/ADM8695 can be configured for
a fixed timeout period—short (100 ms) or long (1.6 sec)—or for
an adjustable timeout period. Some systems are unable to service
the watchdog timer immediately after a reset; in this case, if the
short period is selected for the ADM8691/ADM8695, the device
automatically selects the long timeout period directly after a
reset is issued. The watchdog timer is restarted at the end of a
reset, regardless of whether the reset was caused by lack of
activity on WDI or by V
CC
falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after
RESET
has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur by the end of the minimum timeout period. If WDI
remains permanently high or low, reset pulses are issued after
each long (1.6 sec) timeout period. The watchdog monitor can
be deactivated by allowing the watchdog input (WDI) to float
or by connecting it to midsupply.
On the ADM8690 the watchdog timeout period is fixed at
1.6 sec, and the reset pulse width is fixed at 50 ms. The ADM8691/
ADM8695 allow these times to be adjusted, as shown in Table 5.
Figure 17, Figure 18, Figure 19, and Figure 20 show the various
oscillator configurations that can be used to adjust the reset pulse
width and watchdog timeout period.
WDI
WDO
RESET
t
2
t
1
t
1
t
3
t
1
t
1
= RESET TIME
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
00093-007
Figure 16. Watchdog Timeout Period and Reset Active Time
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects either the 1.6 sec watch-
dog timeout period or the 100 ms watchdog timeout period.
When OSC IN is connected high or left floating, the 1.6 sec
timeout period is selected; when OSC IN is connected low, the
100 ms timeout period is selected. In either case, the timeout
period is 1.6 sec immediately after a reset. This gives the micro-
processor time to reinitialize the system. If OSC IN is low, the
100 ms watchdog timeout period becomes effective after the
first transition of WDI. The software should be written such
that the input/output port driving WDI is left in its power-up
reset state until the initialization routines are completed and the
microprocessor is able to toggle WDI at the minimum watchdog
timeout period of 70 ms.
Table 5. ADM8691 and ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period Reset Active Period
OSC SEL OSC IN Normal Immediately After Reset ADM8691 ADM8695
Low
1
External clock input 1024 CLKs 4096 CLKs 512 CLKs 2048 CLKs
Low
1
External capacitor 400 ms × C/47 pF 1.6 sec × C/47 pF 200 ms × C/47 pF 520 ms × C/47 pF
Floating or high Low 100 ms 1.6 sec 50 ms 200 ms
Floating or high Floating or high 1.6 sec 1.6 sec 50 ms 200 ms
1
When the OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with an external capacitor is f
OSC
(Hz) = 184,000/C (pF).