Datasheet

Data Sheet ADM8690/ADM8691/ADM8695
Rev. C | Page 13 of 24
WATCHDOG OUTPUT (WDO) ( / ) ADM8691 ADM8695
The watchdog output (
WDO
pin on the / )
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input.
ADM8691 ADM8695
WDO
is also set high when V
CC
goes
below the reset threshold.
8
7
OSC SEL
OSC IN
ADM8691/
ADM8695
CLOCK
0 TO 500kHz
00093-008
Figure 17. External Clock Source
8
7
C
OSC
00093-009
OSC SEL
OSC IN
ADM8691/
ADM8695
Figure 18. External Capacitor
NC
NC
8
7
00093-010
OSC SEL
OSC IN
ADM8691/
ADM8695
Figure 19. Internal Oscillator (1.6 Second Watchdog)
NC
8
7
00093-011
OSC SEL
OSC IN
ADM8691/
ADM8695
Figure 20. Internal Oscillator (100 ms Watchdog)
CE GATING AND RAM WRITE PROTECTION
( / ) ADM8691 ADM8695
The ADM8691/ADM8695 include memory protection circuitry
that ensures the integrity of data in memory by preventing write
operations when V
CC
is at an invalid level. Two additional pins
(
CE
IN
and
CE
OUT
) can be used to control the chip enable or write
inputs of CMOS RAM. When V
CC
is present,
CE
OUT
is a buffered
replica of
CE
IN
, with a 3 ns propagation delay. When V
CC
falls
below the reset voltage threshold or V
BATT
, an internal gate forces
CE
OUT
high, independent of
CE
IN
.
CE
OUT
typically drives the
CE
,
CS
, or write input of battery
backed-up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an
invalid level. Similar protection of EEPROMs can be achieved
using the
CE
OUT
pin to drive the store or write inputs.
ADM8691/
ADM8695
CE
OUT
V
CC
LOW = 0
V
CC
OK = 1
C
E
IN
00093-012
Figure 21. Chip Enable Gating
RESET
LOW LINE
V1
V2V2
V1
V
CC
t
1
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
CE
IN
CE
OUT
0
0093-013
Figure 22. Chip Enable Timing