Datasheet

ADM8690/ADM8691/ADM8695 Data Sheet
Rev. C | Page 8 of 24
Pin No.
8-Lead 16-Lead Mnemonic Description
7 15
RESET
Logic Output. RESET goes low if V
CC
falls below the reset threshold or if the watchdog timer is not
serviced within its timeout period. The reset threshold is typically 4.65 V. RESET
remains low for
50 ms ( / ) or 200 ms ( ) after V
CC
returns above the threshold. ADM8690 ADM8691 ADM8695 RESET
also goes low for 50 ms ( / ) or 200 ms ( ) if the watchdog timer is
enabled but not serviced within its timeout period. The
ADM8690 ADM8691 ADM8695
RESET
pulse width can be adjusted on
the / , as shown in . The ADM8691 ADM8695 Table 5 RESET output has an internal 3 µA pull-up and
can either connect to an open-collector reset bus or directly drive a CMOS gate without an
external pull-up resistor.
N/A 16 RESET
Logic Output. RESET is an active high output. It is the inverse of RESET
.